Research Papers

Hot Spot Cooling and Harvesting Central Processing Unit Waste Heat Using Thermoelectric Modules

[+] Author and Article Information
Soochan Lee

School for Engineering of Matter,
Transport and Energy,
Arizona State University,
501 E Tyler Mall, ECG 303,
Tempe, AZ 85287

Patrick E. Phelan

School for Engineering of Matter,
Transport and Energy,
Arizona State University,
501 E Tyler Mall, ECG 303,
Tempe, AZ 85287
e-mail: phelan@asu.edu

Carole-Jean Wu

School of Computing, Informatics, and
Decision Systems Engineering,
Arizona State University,
660 S. Mill Avenue,
Centerpoint Building 203-09,
Tempe, AZ 85251

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 26, 2014; final manuscript received May 25, 2015; published online June 8, 2015. Assoc. Editor: Ronggui Yang.

J. Electron. Packag 137(3), 031010 (Sep 01, 2015) (9 pages) Paper No: EP-14-1118; doi: 10.1115/1.4030686 History: Received December 26, 2014; Revised May 25, 2015; Online June 08, 2015

The increasing integration of high performance processors and dense circuits in current computing devices has produced high heat flux in localized areas (hot spots), which limits their performance and reliability. To control the hot spots on a central processing unit (CPU), many researchers have focused on active cooling methods such as thermoelectric coolers (TECs) to avoid thermal emergencies. This paper presents optimized thermoelectric modules on top of the CPU combined with a conventional air-cooling device to reduce the core temperature and at the same time harvest waste heat energy generated by the CPU. To control the temperature of the cores, we attach small-sized TECs to the CPU and use thermoelectric generators (TEGs) placed on the rest of the CPU to convert waste heat energy into electricity. This study investigates design alternatives with an analytical model considering the nonuniform temperature distribution based on two-node thermal networks. The results indicate that we are able to attain more energy from the TEGs than energy consumption for running the TECs. In other words, we can allow the harvested heat energy to be reused to power other components and reduce cores temperature simultaneously. Overall, the idea of simultaneous core cooling and waste heat harvesting using thermoelectric modules on a CPU is a promising method to control the problem of heat generation and to reduce energy consumption in a computing device.

Copyright © 2015 by ASME
Your Session has timed out. Please sign back in to continue.



Grahic Jump Location
Fig. 1

Infrared (IR) image for an active computing system (Intel Core i5 3470 processor) running 400.perlbench benchmark

Grahic Jump Location
Fig. 2

Architecture—lidded electronic packaging with TEG [5,6]

Grahic Jump Location
Fig. 3

(a) Thermal resistance network of heat flow in electronic packaging and (b) schematic diagram of two-node thermal network

Grahic Jump Location
Fig. 4

(a) Calculated temperature difference between hot and cold sides of a TEG based on the performance counter measurement. (b) The theoretical power output of the TEG as a function of time based on Eq. (8). The CPU load (∼5 W) is generated by running 400.perlbench in the SPEC2006 CPU benchmark suite on an Intel Core i5 3470 processor.

Grahic Jump Location
Fig. 5

CPU temperature running 400.perlbench spec benchmark in core 2 measured by a thermocouple and a thermal trace, and calculated by a two-node thermal network analysis

Grahic Jump Location
Fig. 6

Core temperature measurement (°C) of core 0 inside CPU case using an IR camera running 400.perlbench benchmark

Grahic Jump Location
Fig. 7

(a) Temperature distribution measured with thermocouples of the CPU case with a 3 cm × 3 cm-sized TEG using 400.perlbench application in core 2. (b) An IR image of the CPU case with 400.perlbench application in core 2. (c) Schematic of the proposed TECs- and TEGs-based CPU from the measured IR image and thermocouples in Figs. 7(a) and 7(b).

Grahic Jump Location
Fig. 8

(a) Thermal resistance network of heat flow in electronic packaging with TEGs and TECs, and calculated power generation from the TEGs in the configuration of Fig. 7(c)

Grahic Jump Location
Fig. 9

CPU temperature when executing the 400.perlbench benchmark in core 2 measured with the hardware performance monitoring counters. Horizontal dotted lines represent the targeted temperature for cooling. In this case, 70 °C is the target temperatures under our evaluation to increase the reliability of the CPU.

Grahic Jump Location
Fig. 10

CPU core temperatures versus sweeping current: (a) with 3.3 mm thick TEG and TEC and (b) with 0.8 mm thick TEG and TEC when executing the 400.perlbench benchmark




Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In