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Research Papers

Mixed Array of Compliant Interconnects to Balance Mechanical and Electrical Characteristics

[+] Author and Article Information
R. I. Okereke

Mem. ASME
Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
813 Ferst Drive,
Atlanta, GA 30332

S. K. Sitaraman

Fellow ASME
Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
813 Ferst Drive,
Atlanta, GA 30332

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 13, 2014; final manuscript received March 14, 2015; published online April 17, 2015. Assoc. Editor: Tong Cui.

J. Electron. Packag 137(3), 031006 (Sep 01, 2015) (9 pages) Paper No: EP-14-1030; doi: 10.1115/1.4030065 History: Received March 13, 2014; Revised March 14, 2015; Online April 17, 2015

Various designs of compliant interconnects are being pursued in universities and industry to accommodate the coefficient of thermal expansion (CTE) mismatch between die and substrate or substrate and board. Although such interconnects are able to mechanically decouple the components, electrical parasitics of compliant interconnects are often high compared to the electrical parasitics of solder bump or solder ball interconnects. This increase in electrical parasitics is due to the fact that compliant interconnects typically having longer path lengths and smaller cross-sectional areas to provide compliance, which in turn, increases their electrical parasitics. In this paper, we present a mixed array of compliant interconnects as a tradeoff between mechanical compliance and electrical parasitics. In the proposed implementation, the die area is subdivided into three regions where high compliance, medium-compliance, and low-compliance interconnect variants are situated in the outer, middle, and inner regions of the die, respectively. By introducing the low-compliance variants into the assembly, interconnects with greatly reduced electrical parasitics can be used as power/ground interconnects, while the high-compliance interconnects, situated near the die edges, can be used as signal interconnects. This paper demonstrates the implementation of this configuration and also presents the experimental characterization of such heterogeneous array of interconnects.

Copyright © 2015 by ASME
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References

Figures

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Fig. 7

First principal stress (MPa) in die at room temperature

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Fig. 6

Strip model of heterogeneous interconnect layout (die hidden)

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Fig. 5

Inductance (pH) as a function of beam dimensions in μm (legend shows different beam thickness values)

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Fig. 4

Electrical resistance (mΩ) as a function of interconnect dimensions in μm (legend shows different beam thickness values)

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Fig. 3

Fatigue life (number of thermal cycles) as a function of beam dimensions in μm (legend shows different beam thickness values)

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Fig. 2

In-plane compliance (mm/N) as a function of beam dimensions in μm (legend shows different beam thickness values)

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Fig. 1

(a) Topographical layout of heterogeneous implementation and (b) mask design

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Fig. 8

First principal die stresses and die warpage of a solder bump package

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Fig. 9

Out-of-plane die nodal displacement (mm) at room temperature

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Fig. 10

Elemental accumulated total strain range of the third stabilized thermal cycle

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Fig. 11

Accumulated total strain range comparison in a heterogeneous array package

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Fig. 12

Interconnect photomask layout for heterogeneous die

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Fig. 13

Fabricated interconnects

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Fig. 15

Load versus displacement plot to determine out-of-plane compliance

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Fig. 14

Captured image from four wire resistance measurement setup

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