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Research Papers

Multiscale Transient Thermal Analysis of Microelectronics

[+] Author and Article Information
Banafsheh Barabadi

Department of Mechanical Engineering,
Massachusetts Institute of Technology,
77 Massachusetts Avenue,
Cambridge, MA 02139

Satish Kumar

George W. Woodruff School
of Mechanical Engineering,
Georgia Institute of Technology,
801 Ferst Drive,
Atlanta, GA 30332

Valeriy Sukharev

Design-to-Silicon,
Mentor Graphics Corporation,
46871 Bayside Parkway,
Fremont, CA 94538

Yogendra K. Joshi

George W. Woodruff School
of Mechanical Engineering,
Georgia Institute of Technology,
801 Ferst Drive,
Atlanta, GA 30332
e-mail: yogendra.joshi@me.gatech.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 2, 2013; final manuscript received February 16, 2015; published online April 16, 2015. Assoc. Editor: Amy Fleischer.

J. Electron. Packag 137(3), 031002 (Sep 01, 2015) (8 pages) Paper No: EP-13-1037; doi: 10.1115/1.4029835 History: Received May 02, 2013; Revised February 16, 2015; Online April 16, 2015

In a microelectronic device, thermal transport needs to be simulated on scales ranging from tens of nanometers to hundreds of millimeters. High accuracy multiscale models are required to develop engineering tools for predicting temperature distributions with sufficient accuracy in such devices. A computationally efficient and accurate multiscale reduced order transient thermal modeling methodology was developed using a combination of two different approaches: “progressive zoom-in” method and “proper orthogonal decomposition (POD)” technique. The capability of this approach in handling several decades of length scales from “package” to “chip components” at a considerably lower computational cost, while maintaining satisfactory accuracy was demonstrated. A flip chip ball grid array (FCBGA) package was considered for demonstration. The transient temperature and heat fluxes calculated on the top and bottom walls of the embedded chip at the package level simulations are employed as dynamic boundary conditions for the chip level simulation. The chip is divided into ten function blocks. Randomly generated dynamic power sources are applied in each of these blocks. The temperature rise in the different layers of the chip calculated from the multiscale model is compared with a finite element (FE) model. The close agreement between two models confirms that the multiscale approach can predict temperature rise accurately for scenarios corresponding to different power sources in functional blocks, without performing detailed FE simulations, which significantly reduces computational effort.

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Figures

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Fig. 1

Flowchart of the hybrid scheme for multiscale thermal modeling

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Fig. 3

Spatial distribution of temperature rise extracted from FE method after 1 s for (a) FCBGA package and (b) chip

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Fig. 4

2D contour plots of the first four POD modes at z = 1.33 mm from the bottom of the package; this plane crosses the center of die

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Fig. 5

Dynamic randomly generated power profile for function blocks 1, 2, 10 (a–c) and randomly generated total chip power (d)

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Fig. 6

Spatial distribution of temperature rise at 1 s extracted from the POD model (a) and FE simulation (c). The domain is sliced vertically along XZ plane. The right-most slice is the A–A cross section (b).

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Fig. 7

Comparison of temporal dependence of temperature rise between FE (markers) and POD (solid lines) models at four different points (a) and the corresponding randomly generated total chip power (b)

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Fig. 8

Transient temperature distribution at the interface of device and interconnect/dielectric layers: t = 0, 0.2, 0.4, 0.6, 0.85, and 0.95 s

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