Research Papers

Sequential Reflow-Process Optimization to Reduce Die-Attach Solder Voids

[+] Author and Article Information
Youmin Yu

Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: youminy@qti.qualcomm.com

Victor Chiriac

Qualcomm Technologies, Inc.,
5775 Morehouse Drive,
San Diego, CA 92121
e-mail: vchiriac@qti.qualcomm.com

Yingwei Jiang

Freescale Semiconductor (China) Limited,
No. 15 Xinghua Avenue,
Xiqing Economic Development Area,
Tianjin 300385,China
e-mail: r37110@freescale.com

Zhijie Wang

Xiqing Economic Development Area,
No. 15 Xinghua Avenue,
Tianjin 300385,China
e-mail: r14985@freescale.com

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 26, 2013; final manuscript received January 7, 2015; published online January 30, 2015. Assoc. Editor: Paul Conway.

J. Electron. Packag 137(2), 021013 (Jun 01, 2015) (8 pages) Paper No: EP-13-1015; doi: 10.1115/1.4029569 History: Received February 26, 2013; Revised January 07, 2015; Online January 30, 2015

Solder voids are detrimental to the thermal, mechanical, and reliability performance of integrated circuit (IC) packages and must be controlled within certain specifications. A sequential method of optimizing solder-reflow process to reduce die-attach solder voids in power quad flat no-lead (QFN) packages is presented. The sequential optimization consists, in turn, of theoretical prediction, heat transfer comparison, and experimental validation. First, the theoretical prediction uses calculations to find the optimal pause location and time for a lead frame strip (with dies bonded to it by solder paste) to receive uniform heat transfer during the solder-reflow stage. Next, reflow profiles at different locations on the lead frame strip are measured. Heat transfer during the reflow stage at these locations is calculated from the measured reflow profiles and is compared to each other to confirm the theoretical prediction. Finally, only a minimal number of actual trials are conducted to verify the predicted and confirmed optimal process. Since the theoretical prediction and heat transfer comparison screens out most of the unnecessary trials which must be conducted in common design of experiment (DoE) and trial-and-error methods, the sequential optimization method saves significant time and cost.

Copyright © 2015 by ASME
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Fig. 1

Diagram of lead frame, dies, and leads of the power QFN package

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Fig. 2

Schematic of the reflow oven: (a) side view and (b) top view

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Fig. 3

Close relation between heater blocks 3 and 4 and the reflow stage, shown by the two dashed lines. The upper part is the side view of the reflow oven; the bottom part is a reflow profile.

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Fig. 4

Predicted lead frame locations under each transport index: (a) I = 13; (b) I = 14; and (c) I = 15

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Fig. 5

Distribution of the four thermocouples (TCs) on the lead frame strip

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Fig. 6

A set of simultaneously measured reflow temperature profiles. Within the box, from bottom to top, the profiles are TC1, TC2, TC3, and TC4, respectively.

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Fig. 7

Distribution of the relative heat transfer across the lead frame for I = 13, 14, and 15. The cross circles show mean at each location on the lead frame strip.

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Fig. 8

An X-ray picture of a power QFN sample and solder voids

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Fig. 9

Measured solder void data of the first trial. The cross circles show the mean under each index.

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Fig. 10

One-way analysis of variance (ANOVA) analysis of the solder void data of the first trial

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Fig. 11

Measured solder void data of the second trial

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Fig. 12

One-way ANOVA analysis of the solder void data of the second trial




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