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Research Papers

Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack

[+] Author and Article Information
R. W. Johnson

Department of Mechanical Engineering,
University of New Mexico,
Albuquerque, NM 87131

Y.-L. Shen

Department of Mechanical Engineering,
University of New Mexico,
Albuquerque, NM 87131
e-mail: shenyl@unm.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received April 15, 2014; final manuscript received December 4, 2014; published online January 21, 2015. Assoc. Editor: Shidong Li.

J. Electron. Packag 137(2), 021011 (Jun 01, 2015) (11 pages) Paper No: EP-14-1045; doi: 10.1115/1.4029345 History: Received April 15, 2014; Revised December 04, 2014; Online January 21, 2015

A numerical assessment on the thermal stress in a three-dimensional (3D) microelectronic package structure is performed. The objectives are to study how the chip stack/microbump assembly responds to thermal mismatch induced deformation, and its influences on the electrical performance of devices. The 3D finite element model features a copper through-silicon-via (TSV)/microbump bonding structure connecting two adjacent silicon chips, with and without an underfill layer in between. A case that the entire solder layer has been transformed into an intermetallic layer is also considered. Potential for damage initiation is examined by the measure of stress and strain patterns. It was found that the part of TSV well inside the silicon chip is under high triaxial tensile stresses after thermal cooling, and plastic deformation in copper occurs in and around the microbump regions. The existence of underfill increases plastic strains in the solder joint. The underfill also leads to a significant change in local stress field when the soft solder is transformed entirely into an intermetallic layer. The carrier mobility for the p- and n-type devices is influenced by the stresses in silicon near the TSV; the sizes of “keep-out zone” for the various model configurations are also quantified.

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Figures

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Fig. 1

Representative 3D integration scheme showing vertical stacking of Si chips containing copper TSVs. The schematic is not to scale, and the possible underfill material and other peripheral structures are not included.

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Fig. 2

Finite element model of a representative TSV/microbump bonding structure connecting two adjacent silicon chips, with an underfill layer around the joint region. The dashed line represents the path along which the stress profiles and carrier mobility changes are shown in Sec. 3.3.

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Fig. 3

Finite element mesh (a) without and (b) with an underfill layer. (c) Comparison of the σzz stress profiles in Si, along the dashed line shown in Fig. 2, based on three different finite element meshes for the model without underfill. Meshes 2 and 3 are coarser than mesh 1 (used in the current model); the representative element sizes in meshes 2 and 3 are approximately 1.6 and 2.8 times, respectively, that in mesh 1.

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Fig. 4

Contour plots of stress σxx in the structure (a) without and (b) with the underfill

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Fig. 5

Contour plots of stress σyy in the structure (a) without and (b) with the underfill

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Fig. 6

Contour plots of stress σzz in the structure (a) without and (b) with the underfill

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Fig. 7

Contour plots of hydrostatic stress in the structure (a) without and (b) with the underfill

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Fig. 8

Contour plots of stress σxy in the structure (a) without and (b) with the underfill

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Fig. 9

Contour plots of equivalent plastic strain in the structures (a) without and (b) with the underfill

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Fig. 10

Contour plots of (a) stress σxx and (b) equivalent plastic strain in the structures without underfill, when the solder alloy is replaced by the intermetallic

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Fig. 11

Contour plots of stresses (a) σxx, (b) σyy, (c) σzz, (d) σxy, and (e) equivalent plastic strain in the structure with underfill, when the solder alloy is replaced by the intermetallic

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Fig. 12

Stress profiles in Si along the x-direction (the dashed line in Fig. 2, at 1.5 μm below the Si surface) for the case of soft solder joint (a) without underfill and (b) with underfill

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Fig. 13

Stress profiles in Si along the x-direction (the dashed line in Fig. 2, at 1.5 μm below the Si surface) for the case of intermetallic joint (a) without underfill and (b) with underfill

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Fig. 14

Fractional carrier mobility change in Si along the x-direction (the dashed line in Fig. 2) for the cases of (a) p-MOSFET and (b) n-MOSFET. Reference lines corresponding to the carrier mobility change of ±5% are also shown.

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Fig. 15

Stress profiles in Si along the x-direction (the dashed line in Fig. 2, at 1.5 μm below the Si surface) for the case of soft solder joint (a) without underfill and (b) with underfill, when all materials in the model are treated as purely elastic

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Fig. 16

Contour plots of equivalent plastic strain in the structure without underfill, when the cooling rate is (a) 100 °C/s and (b) 1 °C/s. Here, the viscoplastic behavior of solder is considered in the modeling.

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Fig. 17

Contour plots of equivalent plastic strain in the structure with underfill, when the cooling rate is (a) 100 °C/s and (b) 1 °C/s. Here, the viscoplastic behavior of solder is considered in the modeling.

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