0
Journal of Electronic Packaging | Volume 137 | Issue 2 | research-article
Research Papers

Thermal Cycling Study of Quilt Packaging

[+] Author and Article Information
M. Ashraf Khan

Visiting Assistant Professor
Electrical and Computer Engineering Department,
Jackson State University,
Jackson, MS 39217
e-mail: mkhan3@alumni.nd.edu

Quanling Zheng

Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: qzheng@nd.edu

David Kopp

Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: kopp.dave@gmail.com

Wayne Buckhanan

Assistant Professor
Department of Computer Science,
Pacific Union College,
One Angwin Avenue,
Angwin, CA 94508
e-mail: waynebuckhanan@alumni.nd.edu

Jason M. Kulick

Indiana Integrated Circuits, LLC,
South Bend, IN 46617
e-mail: jason.kulick@indianaic.com

Patrick Fay

Professor
Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: pfay@nd.edu

Alfred M. Kriman

Visiting Professor
Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: alfred.m.kriman.1@nd.edu

Gary H. Bernstein

Frank M. Freimann Professor
of Electrical Engineering
Department of Electrical Engineering,
University of Notre Dame,
Notre Dame, IN 46556
e-mail: bernstein.1@nd.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 30, 2014; final manuscript received November 23, 2014; published online January 19, 2015. Assoc. Editor: Yi-Shao Lai.

J. Electron. Packag 137(2), 021008 (Jun 01, 2015) (7 pages) Paper No: EP-14-1057; doi: 10.1115/1.4029245 History: Received May 30, 2014; Revised November 23, 2014; Online January 19, 2015
Article
References
Figures
Tables

The continued progress of micro-electronics often requires functionality that is spread across multiple chips. This need has led to the development of a variety of alternative chip-packaging technologies that offer increased speed and bandwidth, with lower losses, in an increasing number of interchip interconnects. One recent alternative is quilt packaging® (QP), which has already shown promise from a performance perspective. The geometry of QP is essentially lateral: large numbers of ultrawide-bandwidth interchip interconnects (superconnects) are made directly by nodules fabricated along the edges of adjacent chips. Metallurgical bonding of the nodules creates a system in the form of a “quilt” of separately manufactured chips. This new interconnect geometry is subject to stresses that are different from more conventional schemes. For example, the thermal stress that causes fatigue and lead to failure in ball grid arrays is essentially shear stress, whereas the most critical stresses in QP are tensile and compressive. This paper describes studies of fatigue failure in QP, with attention to critical high-stress regions previously identified by finite-element modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 °C to 125 °C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focused-ion-beam cross-sectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.
FIGURES IN THIS ARTICLE
<>
Copyright © 2015 by ASME
Your Session has timed out. Please sign back in to continue.

References

1
ITRS, 2009, “The International Technology Roadmap for Semiconductors,” Assembly and Packaging, Semiconductor Industry Association (SIA), Washington, D.C., p. 27.
2
Kouzaev, G. A., 2012, Applications of Advanced Electromagnetics: Components and Systems, Springer, New York, pp. 209–210.
3
Dorf, R. C., 1997, The Electrical Engineering Handbook, 2nd ed., CRC Press, Boca Raton, FL, pp. 851–853.
4
Bernstein, G. H., Liu, Q., Yan, M., Sun, Z., Kopp, D., Porod, W., Snider, G., and Fay, P., 2007, “Quilt Packaging: High-Density, High-Speed Interchip Communications,” IEEE Trans. Adv. Packag., 30(4), pp. 731–740. [CrossRef]
5
Liu, Q., Fay, P., and Bernstein, G. H., 2007, “A Novel Scheme for Wide Bandwidth Chip-to-Chip Communications,” Int. Microelectron. Packag. Soc., 4(1), pp. 1–7.
6
Kulick, J. M., and Bernstein, G. H., 2012, “Quilt Packaging: A Revolutionary and Flexible Approach to High-Performance System in Package,” Adv. Microelectron., 30(2), pp. 12–16.
7
Burghartz, J. N., 2011, Ultra-Thin Chip Technology and Applications, Springer, New York, pp. 47–49. [CrossRef]
8
Fay, P., Kopp, D., Liang, C., Kulick, J. M., Khan, M., and Bernstein, G. H., 2009, “Quilt Packaging of RF Systems With Ultrawide Bandwidths,” Proceedings of the IMAPS—Advanced Technology Workshop on RF and Microwave Packaging, San Diego, CA, pp. 1–5.
9
Kopp, D., Khan, M. A., Kulick, J. M., Kriman, A. M., Fay, P., and Bernstein, G. H., 2010, “Quilt Packaging: Electrical and Thermal Performance Study,” Proceedings of the IMAPS International Conference and Exhibition on Device Packaging, Scottsdale, AZ, Mar. 9–Mar. 12, pp. 1428–1432.
10
Fay, P. J., Kopp, D. J., Lu, T., Neal, D., Bernstein, G. H., and Kulick, J. M., 2014 “Ultrawide-Bandwidth Chip-to-Chip Interconnects for III-V MMICs,” IEEE Microwave Wireless Compon. Lett., 24(1), pp. 29–31. [CrossRef]
11
Amalu, E. H., and Ekere, N. N., 2012, “Damage of Lead-Free Solder Joints in Flip Chip Assemblies Subjected to High-Temperature Thermal Cycling,” Comput. Mater. Sci., 65, pp. 470–484. [CrossRef]
12
Dudek, R., Döring, R., and Michael, B., 2003 “Reliability Prediction of Area Array Solder Joints,” ASME J. Electron. Packag., 125(4), pp. 562–568. [CrossRef]
13
Suhir, E., 2009, “Predictive Analytical Thermal Stress Modeling in Electronics and Photonics,” ASME Appl. Mech. Rev., 62(4), p. 040801. [CrossRef]
14
Tang, H., and Basaran, C., 2003, “A Damage Mechanics-Based Fatigue Life Prediction Model for Solder Joints,” ASME J. Electron. Packag., 125(1), pp. 120–125. [CrossRef]
15
Tunga, K., and Sitaraman, S. K., 2007, “An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls,” ASME J. Electron. Packag., 129(4), pp. 427–433. [CrossRef]
16
Khan, M. A., Kulick, J. M., Kopp, D., Fay, P., Kriman, A. M., and Bernstein, G. H., 2013, “Design and Robustness of Quilt Packaging Superconnect,” J. Microelectron. Electron. Packag., 10(1), pp. 8–14. [CrossRef]
17
Kopp, D., Khan, M. A., Garvey, S., Anderson, K., Kulick, J., Kriman, A., Bernstein, G. H., and Fay, P. J., 2010, “Quilt Packaging: A Robust Coplanar Chip-to-Chip Interconnect Offering Very High Bandwidth,” Proceedings of the CS MANTECH Conference, Portland, OR, pp. 309–312.
18
Khan, M. A., Kriman, A. M., and Bernstein, G. H., 2010, “Thermal Modeling of Quilt Packaging Interconnects,” Proceedings of the 18th Biennial University/Government/Industry Micro/Nano Symposium (UGIM), West Lafayette, IN, June 28–July 1, pp. 166–168. [CrossRef]
19
Zheng, Q., Kopp, D., Khan, M. A., Fay, P., Kriman, A. M., and Bernstein, G. H., 2014, “Investigation of Quilt Packaging Interchip Interconnect With Solder Paste,” IEEE Trans. Compon., Packag. Manuf. Technol., 4(3), pp. 400–407. [CrossRef]
20
JEDEC Solid State Technology Association, 2009, Temperature Cycling, Standard JESD22-A104D, Arlington, VA, p. 5.
21
IPC-9701A, 2006, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments, IPC, Bannockburn, IL, p. 8.
22
Kwon, Y. W., Luteran, A. M., Didoszak, J. M., and Kwon, A. S., 2012, “Study of Solder/Copper Interface Behavior Under Varying Strain Rates,” ASME J. Electron. Packag., 134(3), p. 0310037. [CrossRef]
23
Boyce, B. L., Brewer, L. N., Neilsen, M. K., and Perricone, M. J., 2011, “On the Strain Rate- and Temperature-Dependent Tensile Behavior of Eutectic Sn–Pb Solder,” ASME J. Electron. Packag., 133(3), p. 031009. [CrossRef]
24
Bhate, D., Chan, D., and Subbarayan, G., 2008, “A Nonlinear Fracture Mechanics Approach to Modeling Fatigue Crack Growth in Solder Joints,” ASME J. Electron. Packag., 130(2), p. 021003. [CrossRef]
25
Guojun, H., Tay, A. A. O., Jing-En, L., and Yiyi, M., 2010, “Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package,” ASME J. Electron. Packag., 132(1), p. 011006. [CrossRef]
26
Bernstein, G. H., Carter, A., and Joy, D. C., 2012, “Do SEII Electrons Really Degrade SEM Image Quality?,” Scanning, 35(1), pp. 1–6. [CrossRef] [PubMed]
27
Khan, M. A., 2014, “Thermomechanical Effects in Quilt Packaging,” Ph.D. thesis, University of Notre Dame, Notre Dame, IN.
28
Lau, J. H., 2006, “Reliability of Lead-Free Solder Joints,” ASME J. Electron. Packag., 128(3), pp. 297–301. [CrossRef]
29
JEDEC Publication, 2014, Foundry Process Qualification Guidelines ( Wafer Fabrication Manufacturing Sites), JEP001A, JEDEC Solid State Technology Association, Arlington, VA, p. 12.
30
Ghaffarian, R., 2000, “Accelerated Thermal Cycling and Failure Mechanisms for BGA and CSP Assemblies,” ASME J. Electron. Packag., 122(4), pp. 335–340. [CrossRef]

Figures

Grahic Jump Location
Fig. 1

Schematic presentation of a three-chip “quilt” embedded in a package lead frame. Here, three chips are interconnected by QP nodules of two different sizes (larger nodules connecting chip 1 to chips 2 and 3, and much smaller nodules between chips 2 and 3), as well as wire bonds from chips 1 and 2 to the package lead frame. (Figure by M. Padberg, courtesy of Indiana Integrated Circuits, LLC.)

+Schematic presentation of a three-chip “quilt” embedded in a package lead frame. Here, three chips are interconnected by QP nodules of two different sizes (larger nodules connecting chip 1 to chips 2 and 3, and much smaller nodules between chips 2 and 3), as well as wire bonds from chips 1 and 2 to the package lead frame. (Figure by M. Padberg, courtesy of Indiana Integrated Circuits, LLC.)
View Large  |  Save Figure  |  Download Slide (.ppt)
Schematic presentation of a three-chip “quilt” embedded in a package lead frame. Here, three chips are interconnected by QP nodules of two different sizes (larger nodules connecting chip 1 to chips 2 and 3, and much smaller nodules between chips 2 and 3), as well as wire bonds from chips 1 and 2 to the package lead frame. (Figure by M. Padberg, courtesy of Indiana Integrated Circuits, LLC.)
Grahic Jump Location
Fig. 2

Nodules on two quilted chips. (a) Two adjacent, “quilted” chips (upper structures) on a layer of epoxy (lightly shaded) on a copper heat spreader on a chip carrier. Along the space between the two chips are multiple metal nodules that effect electrical connections between the chips. (b) A connected nodule pair (close-up of circled region in (a)).

+Nodules on two quilted chips. (a) Two adjacent, “quilted” chips (upper structures) on a layer of epoxy (lightly shaded) on a copper heat spreader on a chip carrier. Along the space between the two chips are multiple metal nodules that effect electrical connections between the chips. (b) A connected nodule pair (close-up of circled region in (a)).
View Large  |  Save Figure  |  Download Slide (.ppt)
Nodules on two quilted chips. (a) Two adjacent, “quilted” chips (upper structures) on a layer of epoxy (lightly shaded) on a copper heat spreader on a chip carrier. Along the space between the two chips are multiple metal nodules that effect electrical connections between the chips. (b) A connected nodule pair (close-up of circled region in (a)).
Grahic Jump Location
Fig. 3

The left nodule of Fig. 2(b) apart from the substrate. Total length, depth, and width are indicated by l, h, and w, respectively. The four surfaces of the nodule (two visible) that are anchored in the substrate are insulated by an oxide layer, shown at back and side of the nodule. The thin tin layer faces away to the upper right.

+The left nodule of Fig. 2(b) apart from the substrate. Total length, depth, and width are indicated by l, h, and w, respectively. The four surfaces of the nodule (two visible) that are anchored in the substrate are insulated by an oxide layer, shown at back and side of the nodule. The thin tin layer faces away to the upper right.
View Large  |  Save Figure  |  Download Slide (.ppt)
The left nodule of Fig. 2(b) apart from the substrate. Total length, depth, and width are indicated by l, h, and w, respectively. The four surfaces of the nodule (two visible) that are anchored in the substrate are insulated by an oxide layer, shown at back and side of the nodule. The thin tin layer faces away to the upper right.
Grahic Jump Location
Fig. 4

Top view of nodules with flat and jigsaw-patterned faces. Upward in the figure represents outward from the chip for each nodule.

+Top view of nodules with flat and jigsaw-patterned faces. Upward in the figure represents outward from the chip for each nodule.
View Large  |  Save Figure  |  Download Slide (.ppt)
Top view of nodules with flat and jigsaw-patterned faces. Upward in the figure represents outward from the chip for each nodule.
Grahic Jump Location
Fig. 5

Cu nodule pairs to microwave superconnects for CPW, where G and S indicate nodules for ground and signal lines, respectively. (a) Ground nodules have one side tapered, and the signal nodule has two sides tapered. (b) Optical micrograph of a CPW QP system [6]. The middle region of reflowed Sn appears dark due to light scattering away from the lens.

+Cu nodule pairs to microwave superconnects for CPW, where G and S indicate nodules for ground and signal lines, respectively. (a) Ground nodules have one side tapered, and the signal nodule has two sides tapered. (b) Optical micrograph of a CPW QP system [6]. The middle region of reflowed Sn appears dark due to light scattering away from the lens.
View Large  |  Save Figure  |  Download Slide (.ppt)
Cu nodule pairs to microwave superconnects for CPW, where G and S indicate nodules for ground and signal lines, respectively. (a) Ground nodules have one side tapered, and the signal nodule has two sides tapered. (b) Optical micrograph of a CPW QP system [6]. The middle region of reflowed Sn appears dark due to light scattering away from the lens.
Grahic Jump Location
Fig. 6

SEM micrograph of two chips with nodules plated and joined by Sn. The two chips are labeled “chip #1” and “chip #2” with their related nodules, nodules #1 and #2. The Sn-joined region is indicated by the dashed rectangle. The nodules are 200 μm wide at the solder joint.

+SEM micrograph of two chips with nodules plated and joined by Sn. The two chips are labeled “chip #1” and “chip #2” with their related nodules, nodules #1 and #2. The Sn-joined region is indicated by the dashed rectangle. The nodules are 200 μm wide at the solder joint.
View Large  |  Save Figure  |  Download Slide (.ppt)
SEM micrograph of two chips with nodules plated and joined by Sn. The two chips are labeled “chip #1” and “chip #2” with their related nodules, nodules #1 and #2. The Sn-joined region is indicated by the dashed rectangle. The nodules are 200 μm wide at the solder joint.
Grahic Jump Location
Fig. 7

Measured thermal cycling profile

+Measured thermal cycling profile
View Large  |  Save Figure  |  Download Slide (.ppt)
Measured thermal cycling profile
Grahic Jump Location
Fig. 8

Result of 500 thermal cycles on a nodule. (a) Before thermal cycling. (b) After 500 thermal cycles. (c) The nodule is rotated 90 deg ccw and tilted at 52 deg away from the viewer. The milled area is indicated by a dashed rectangle. (d) The critical area of the top metal layer is indicated by a circle. The electroplated copper shown is at the back of the nodule. The layer remains intact after 500 cycles.

+Result of 500 thermal cycles on a nodule. (a) Before thermal cycling. (b) After 500 thermal cycles. (c) The nodule is rotated 90 deg ccw and tilted at 52 deg away from the viewer. The milled area is indicated by a dashed rectangle. (d) The critical area of the top metal layer is indicated by a circle. The electroplated copper shown is at the back of the nodule. The layer remains intact after 500 cycles.
View Large  |  Save Figure  |  Download Slide (.ppt)
Result of 500 thermal cycles on a nodule. (a) Before thermal cycling. (b) After 500 thermal cycles. (c) The nodule is rotated 90 deg ccw and tilted at 52 deg away from the viewer. The milled area is indicated by a dashed rectangle. (d) The critical area of the top metal layer is indicated by a circle. The electroplated copper shown is at the back of the nodule. The layer remains intact after 500 cycles.
Grahic Jump Location
Fig. 9

Same views as Fig. 8 for a second nodule after 1000 thermal cycles

+Same views as Fig. 8 for a second nodule after 1000 thermal cycles
View Large  |  Save Figure  |  Download Slide (.ppt)
Same views as Fig. 8 for a second nodule after 1000 thermal cycles
Grahic Jump Location
Fig. 10

Result of thermal cycling of a quilted nodule pair (same as shown in Fig. 6) with both right-angle and oblique corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.

+Result of thermal cycling of a quilted nodule pair (same as shown in Fig. 6) with both right-angle and oblique corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.
View Large  |  Save Figure  |  Download Slide (.ppt)
Result of thermal cycling of a quilted nodule pair (same as shown in Fig. 6) with both right-angle and oblique corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.
Grahic Jump Location
Fig. 11

Effect of thermal cycling on a pair of quilted, 200 μm-wide nodules with only right-angle corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.

+Effect of thermal cycling on a pair of quilted, 200 μm-wide nodules with only right-angle corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.
View Large  |  Save Figure  |  Download Slide (.ppt)
Effect of thermal cycling on a pair of quilted, 200 μm-wide nodules with only right-angle corners. (a) Before thermal cycling. (b) After 500 cycles. (c) After 1000 cycles.

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Understanding the Problem
Design and Application of the Worm Gear> Chapter 12
Start-Up, Shutdown, and Lay-Up
Consensus on Pre-Commissioning Stages for Cogeneration and Combined Cycle Power Plants
Subsection NB—Class 1 Components
Companion Guide to the ASME Boiler & Pressure Vessel Code, Volume 1, Second Edition> Chapter 6
Applicability of the HRA Methods for External Event PSA Based on Simulator Training (PSAM-0337)
Proceedings of the Eighth International Conference on Probabilistic Safety Assessment & Management (PSAM)
Analysis of Components in VIII-2
Guidebook for the Design of ASME Section VIII Pressure Vessels, Third Edition> Chapter 8
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In