ITRS, 2009, “The International Technology Roadmap for Semiconductors,” Assembly and Packaging, Semiconductor Industry Association (SIA), Washington, D.C., p. 27.
Kouzaev, G. A., 2012, Applications of Advanced Electromagnetics: Components and Systems, Springer, New York, pp. 209–210.
Dorf, R. C., 1997, The Electrical Engineering Handbook, 2nd ed., CRC Press, Boca Raton, FL, pp. 851–853.
Bernstein, G. H., Liu, Q., Yan, M., Sun, Z., Kopp, D., Porod, W., Snider, G., and Fay, P., 2007, “Quilt Packaging: High-Density, High-Speed Interchip Communications,” IEEE Trans. Adv. Packag., 30(4), pp. 731–740.
[CrossRef]Liu, Q., Fay, P., and Bernstein, G. H., 2007, “A Novel Scheme for Wide Bandwidth Chip-to-Chip Communications,” Int. Microelectron. Packag. Soc., 4(1), pp. 1–7.
Kulick, J. M., and Bernstein, G. H., 2012, “Quilt Packaging: A Revolutionary and Flexible Approach to High-Performance System in Package,” Adv. Microelectron., 30(2), pp. 12–16.
Burghartz, J. N., 2011,
Ultra-Thin Chip Technology and Applications, Springer, New York, pp. 47–49.
[CrossRef]Fay, P., Kopp, D., Liang, C., Kulick, J. M., Khan, M., and Bernstein, G. H., 2009, “Quilt Packaging of RF Systems With Ultrawide Bandwidths,” Proceedings of the IMAPS—Advanced Technology Workshop on RF and Microwave Packaging, San Diego, CA, pp. 1–5.
Kopp, D., Khan, M. A., Kulick, J. M., Kriman, A. M., Fay, P., and Bernstein, G. H., 2010, “Quilt Packaging: Electrical and Thermal Performance Study,” Proceedings of the IMAPS International Conference and Exhibition on Device Packaging, Scottsdale, AZ, Mar. 9–Mar. 12, pp. 1428–1432.
Fay, P. J., Kopp, D. J., Lu, T., Neal, D., Bernstein, G. H., and Kulick, J. M., 2014 “Ultrawide-Bandwidth Chip-to-Chip Interconnects for III-V MMICs,” IEEE Microwave Wireless Compon. Lett., 24(1), pp. 29–31.
[CrossRef]Amalu, E. H., and Ekere, N. N., 2012, “Damage of Lead-Free Solder Joints in Flip Chip Assemblies Subjected to High-Temperature Thermal Cycling,” Comput. Mater. Sci., 65, pp. 470–484.
[CrossRef]Dudek, R., Döring, R., and Michael, B., 2003 “Reliability Prediction of Area Array Solder Joints,” ASME J. Electron. Packag., 125(4), pp. 562–568.
[CrossRef]Suhir, E., 2009, “Predictive Analytical Thermal Stress Modeling in Electronics and Photonics,” ASME Appl. Mech. Rev., 62(4), p. 040801.
[CrossRef]Tang, H., and Basaran, C., 2003, “A Damage Mechanics-Based Fatigue Life Prediction Model for Solder Joints,” ASME J. Electron. Packag., 125(1), pp. 120–125.
[CrossRef]Tunga, K., and Sitaraman, S. K., 2007, “An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls,” ASME J. Electron. Packag., 129(4), pp. 427–433.
[CrossRef]Khan, M. A., Kulick, J. M., Kopp, D., Fay, P., Kriman, A. M., and Bernstein, G. H., 2013, “Design and Robustness of Quilt Packaging Superconnect,” J. Microelectron. Electron. Packag., 10(1), pp. 8–14.
[CrossRef]Kopp, D., Khan, M. A., Garvey, S., Anderson, K., Kulick, J., Kriman, A., Bernstein, G. H., and Fay, P. J., 2010, “Quilt Packaging: A Robust Coplanar Chip-to-Chip Interconnect Offering Very High Bandwidth,” Proceedings of the CS MANTECH Conference, Portland, OR, pp. 309–312.
Khan, M. A., Kriman, A. M., and Bernstein, G. H., 2010, “Thermal Modeling of Quilt Packaging Interconnects,” Proceedings of the 18th Biennial University/Government/Industry Micro/Nano Symposium (UGIM), West Lafayette, IN, June 28–July 1, pp. 166–168.
[CrossRef]Zheng, Q., Kopp, D., Khan, M. A., Fay, P., Kriman, A. M., and Bernstein, G. H., 2014, “Investigation of Quilt Packaging Interchip Interconnect With Solder Paste,” IEEE Trans. Compon., Packag. Manuf. Technol., 4(3), pp. 400–407.
[CrossRef]JEDEC Solid State Technology Association, 2009, Temperature Cycling, Standard JESD22-A104D, Arlington, VA, p. 5.
IPC-9701A, 2006, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments, IPC, Bannockburn, IL, p. 8.
Kwon, Y. W., Luteran, A. M., Didoszak, J. M., and Kwon, A. S., 2012, “Study of Solder/Copper Interface Behavior Under Varying Strain Rates,” ASME J. Electron. Packag., 134(3), p. 0310037.
[CrossRef]Boyce, B. L., Brewer, L. N., Neilsen, M. K., and Perricone, M. J., 2011, “On the Strain Rate- and Temperature-Dependent Tensile Behavior of Eutectic Sn–Pb Solder,” ASME J. Electron. Packag., 133(3), p. 031009.
[CrossRef]Bhate, D., Chan, D., and Subbarayan, G., 2008, “A Nonlinear Fracture Mechanics Approach to Modeling Fatigue Crack Growth in Solder Joints,” ASME J. Electron. Packag., 130(2), p. 021003.
[CrossRef]Guojun, H., Tay, A. A. O., Jing-En, L., and Yiyi, M., 2010, “Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package,” ASME J. Electron. Packag., 132(1), p. 011006.
[CrossRef]Bernstein, G. H., Carter, A., and Joy, D. C., 2012, “Do SE
II Electrons Really Degrade SEM Image Quality?,” Scanning, 35(1), pp. 1–6.
[CrossRef] [PubMed]Khan, M. A., 2014, “Thermomechanical Effects in Quilt Packaging,” Ph.D. thesis, University of Notre Dame, Notre Dame, IN.
Lau, J. H., 2006, “Reliability of Lead-Free Solder Joints,” ASME J. Electron. Packag., 128(3), pp. 297–301.
[CrossRef]JEDEC Publication, 2014, Foundry Process Qualification Guidelines ( Wafer Fabrication Manufacturing Sites), JEP001A, JEDEC Solid State Technology Association, Arlington, VA, p. 12.
Ghaffarian, R., 2000, “Accelerated Thermal Cycling and Failure Mechanisms for BGA and CSP Assemblies,” ASME J. Electron. Packag., 122(4), pp. 335–340.
[CrossRef]