0
Research Papers

Optimization of Thermoelectric Coolers for Hotspot Cooling in Three-Dimensional Stacked Chips

[+] Author and Article Information
Matthew Redmond

G. W. Woodruff School
of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332
e-mail: mredmond3@gatech.edu

Satish Kumar

G. W. Woodruff School
of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332
e-mail: satish.kumar@me.gatech.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 6, 2014; final manuscript received August 7, 2014; published online October 6, 2014. Assoc. Editor: Madhusudan Iyengar.

J. Electron. Packag 137(1), 011006 (Oct 06, 2014) (6 pages) Paper No: EP-14-1013; doi: 10.1115/1.4028254 History: Received February 06, 2014; Revised August 07, 2014

Three-dimensional (3D) chip stacking architecture is expected to reduce form factor, improve performance, and decrease power consumption in future microelectronics. High power density and nonuniform power distribution in stacked dies are expected to bring significant thermal challenges for 3D packages due to localized hot spots. Embedded thermoelectric coolers (TECs) have potential to provide reliable and localized cooling at these hot spots. In this work, peak package temperature or active cooling per power consumption of TECs are optimized, considering applied current and thickness of TECs as parameters, for a 3D electronic package with two stacked dies. Each die has two hot spots and one TEC is paired with each hot spot. Three different optimization methods are considered in order to ensure a robust solution. The optimization suggests that both the peak temperature in package and energy efficiency of the cooling system can be significantly improved through the optimization of TECs. TECs are also compared against a configuration where they are replaced by copper blocks or thermal vias. A total of 4.7 °C of additional localized cooling is observed using TECs which is beyond what is achievable with copper vias in place of the TECs. The study also suggests that it is better to use TECs to cool only the hottest portions of the package to avoid introducing additional thermal resistance and Joule heating in the package.

FIGURES IN THIS ARTICLE
<>
Copyright © 2015 by ASME
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Fig. 1

Schematic of the electronic package. The computational domain includes the heat spreader, chips, TIM, ERL, infill, hotspots, and TECs [24].

Grahic Jump Location
Fig. 2

Comparison of the hot spot temperature for various applied current magnitudes to the TEC. Results from the model developed in comsol compared against the experimental data and modeling results reported in Refs. [12] and [33].

Grahic Jump Location
Fig. 3

Contour plot of the objective function (maximum temperature) for the temperature only optimization. Maximum temperature (°C) for the optimum point found by the gradient descent method, Luus–Jaakola method, and parametric sweep have been indicated. The y-axis (Ib) is the applied current to the bottom TEC, and the x-axis (tb) is the thickness of the bottom TEC. The dashed line represents the thin region where the lowest maximum temperature occurs, and the top and bottom hot spot temperatures are equal.

Grahic Jump Location
Fig. 4

Intersection of the top and bottom hotspot temperatures in the region of the optimum solution. Ib is the applied current to the bottom TEC, tb is the thickness of the bottom TEC, Tt is the peak temperature on the top chip, and Tb is the peak temperature on the bottom chip.

Grahic Jump Location
Fig. 5

Contour plot of the objective function (active cooling divided by power consumption). Optimum points found by the gradient descent method, Luus–Jaakola method, and parametric sweep have been indicated.

Grahic Jump Location
Fig. 6

The temperature only optimization path for the Luus–Jaakola method using two different criteria is shown on two plots. Two plots are necessary to show the solution path because a total of four independent variables are optimized simultaneously. Two of the four independent variables make-up the axes on each plot. These variables are top TEC current (It, left), bottom TEC current (Ib, left), top TE material thickness (tt, right), and bottom TE material thickness (tb, right). The similar results obtained using different criteria and solution paths gives confidence in the robustness of this solution. The small circles represent intermediate steps and the large circles represent the optimum.

Grahic Jump Location
Fig. 7

Hot spot cooling using TECs in comparison to using 100 μm thick copper blocks in place of all four TECs and the total power consumption in all TECs. The optimums are labeled with the corresponding independent variables. (a) Temperature-only optimization with TECs on the top and bottom. (b) Temperature-only optimization with copper blocks on the top chip and TECs on the bottom chip. (c) Combined temperature and power consumption optimization with copper blocks on the top chip and TECs on the bottom chip. The combined temperature and power consumption optimization with top and bottom TECs (not shown) suggests that the thickness of the top TEC should be zero, which is the same as the result for (c).

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In