0
Technical Brief

A New Analytical Method for Calculating Maximum Junction Temperature of Packaged Devices Incorporating the Temperature Distribution at the Base of the Substrate

[+] Author and Article Information
J. H. L. Ling

Department of Mechanical Engineering,
National University of Singapore,
117576, Singapore
e-mail: g0900551@nus.edu.sg

A. A. O. Tay

Department of Mechanical Engineering,
National University of Singapore,
117576, Singapore
e-mail: mpetayao@nus.edu.sg

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 8, 2013; final manuscript received July 23, 2014; published online October 6, 2014. Assoc. Editor: Mehmet Arik.

J. Electron. Packag 137(1), 014502 (Oct 06, 2014) (6 pages) Paper No: EP-13-1133; doi: 10.1115/1.4028120 History: Received December 08, 2013; Revised July 23, 2014

All current analytical methods for calculating junction temperature of field effect transistor (FET) and monolithic microwave integrated circuits (MMIC) devices have assumed a constant uniform temperature at the base of the substrate. In a packaged device, however, where the substrate is attached to a carrier, finite element thermal analyses have shown that the temperature distribution along the base of the substrate is not uniform but has a bell-shaped distribution. Consequently, current analytical methods which attempt to predict the junction temperature of a packaged MMIC device by assuming a constant uniform temperature at the base of the substrate have been found to be inaccurate. In this paper, it is found that the temperature distribution along the base of a substrate can be well approximated by a Lorentz distribution which can be determined from a few basic parameters of the device such as the gate length, gate pitch, number of gates, and length of substrate. By incorporating this Lorentz temperature distribution at the base of the substrate with a new closed-form solution for the three-dimensional temperature distribution within the substrate, a new analytical method is developed for accurately calculating the junction temperature of MMIC devices. The accuracy of this new method has been verified with junction temperatures of MMIC devices measured using thermoreflectance thermography (TRT) as well as those calculated using finite element analysis (FEA).

FIGURES IN THIS ARTICLE
<>
Copyright © 2015 by ASME
Your Session has timed out. Please sign back in to continue.

References

Chang, S. K., Jin, C. J., Dong, P. C., and In, B. Y., 2005, “Thermal Characterization of MMIC by Numerical Analysis,” Asia-Pacific Microwave Conference (APMC 2005), Suzhou, China, December 4–7. [CrossRef]
Li, L., Coccioli, R., Nary, K., and Canfield, P., 2005, “Multi-Scale Thermal Analysis of GaAs RF Device,” IEEE 21st Annual Semiconductor Thermal Measurement and Management Symposium, San Jose, CA, March 15–17, pp. 259–263 [CrossRef].
Wilson, J., and Decker, K., 1994, “GaAs MMIC Thermal Modeling for Channel Temperatures in Accelerated Life Test Fixtures and Microwave Modules,” IEEE/CPMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM X), San Jose, CA, February 1–3, pp. 121–128 [CrossRef].
Wright, J. L., Marks, B. W., and Decker, K. D., 1991, “Modeling of MMIC Devices for Determining MMIC Channel Temperatures During Life Tests,” IEEE Seventh Annual Semiconductor Thermal Measurement and Management Symposium(SEMI-THERM VII), IEEE, Phoenix, AZ, February 12–14, pp. 131–139 [CrossRef].
Lindsted, R. D., and Surty, R. J., 1972, “Steady-State Junction Temperatures of Semiconductor Chips,” IEEE Trans. Electron Devices, 19(1), pp. 41–44. [CrossRef]
Gao, G. B., Wang, M. Z., Gui, X., and Morkoc, H., 1989, “Thermal Design Studies of High-Power Heterojunction Bipolar Transistors,” IEEE Trans. Electron Devices, 36(5), pp. 854–863. [CrossRef]
Lee, C. C., Palisoc, A. L., and Min, Y. J., 1989, “Thermal Analysis of Integrated Circuit Devices and Packages,” IEEE Trans. Compon. Hybrids Manuf. Technol., 12(4), pp. 701–709. [CrossRef]
Ditri, J., 2007, “Heat Conduction in Microwave Devices With Orthotropic and Temperature-Dependent Thermal Conductivity,” IEEE Trans. Microwave Theory Tech., 55(3), pp. 555–560. [CrossRef]
Kokkas, A. G., 1974, “Thermal Analysis of Multiple-Layer Structures,” IEEE Trans. Electron Devices, 21(11), pp. 674–681. [CrossRef]
Smith, D. H., 1991, “Predicting Operating Temperatures for GaAs ICs,” 13th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, Monterey, CA, October 20–23, pp. 187–190 [CrossRef].
Haji-Sheikh, A., 1990, “Peak Temperature in High-Power Chips,” IEEE Trans. Electron Devices, 37(4), pp. 902–907. [CrossRef]
Darwish, A. M., Bayba, A. J., and Hung, H. A., 2005, “Accurate Determination of Thermal Resistance of FETs,” IEEE Trans. Microwave Theory Tech., 53(1), pp. 306–313. [CrossRef]
Decker, S. K. K., and Rosato, D., 2005, “Thermal Characterization of GaAs FETs,” Application Notes of TriQuint Semiconductor and Harvard Thermal Inc and Case Studies in Coolingzone.com, December, available at: http://www.coolingzone.com/library.php?read=468
Vijayakumar, B., Burton, R., and Guo, Y., 2004, “Device and Package Level Thermal Modeling of GaAs Power Amplifiers,” 9th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM '04), Las Vegas, NV, June 1–4, Vol. 1, pp. 291–296 [CrossRef].
Harris, T. R., Melamed, S., Luniya, S., Davis, W. R., Steer, M. B., Doxsee, L. E., Obermiller, K., and Hawkinson, C., 2010, “Thermal Analysis and Verification of a Mounted Monolithic Integrated Circuit,” IEEE SoutheastCon 2010: Energizing Our Future, Concord, NC, March 18–21, pp. 37–40 [CrossRef].
Lee, S., Song, S., Au, V., and Moran, K. P., 1995, “Constriction/Spreading Resistance Model for Electronics Packaging,” 4th ASME/JSME Thermal Engineering Joint Conference, Lahaina, HI, March 19–24, Vol. 4, pp. 199–206.
Masana, F. N., 2001, “A New Approach to the Dynamic Thermal Modelling of Semiconductor Packages,” Microelectron. Reliab., 41(6), pp. 901–912 [CrossRef].
Ling, J. H. L., and Tay, A. A. O., 2014, “A New Accurate Closed-Form Analytical Solution for Junction Temperature of High-Powered Devices,” ASME J. Electron. Packag., 136(1), p. 011007 [CrossRef].
Negus, K. J., Franklin, R. W., and Yovanovich, M. M., 1989, “Thermal Modeling and Experimental Techniques for Microwave Bipolar Devices,” IEEE Trans. Compon. Hybrids Manuf. Technol., 12(4), pp. 680–689. [CrossRef]
Leturcq, P., Dorkel, J. M., Napieralski, A., and Lachiver, E., 1987, “A New Approach to Thermal Analysis of Power Devices,” IEEE Trans. Electron Devices, 34(5), pp. 1147–1156. [CrossRef]
Ling, J. H. L., Tay, A. A. O., Choo, K. F., and Chen, W., 2012, “Thermal Characterization and Modelling of a Gallium Arsenide Power Amplifier MMIC,” 13th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), San Diego, CA, May 30–June 1, pp. 440–445. [CrossRef]
Rosato, D., Decker, K., and Ko, S., 2001, “Thermal Characterization Techniques for GaAs FETs,” EE Times Asia, October 1, 1–3. http://www.eetasia.com/ART_8800142572_499501_TA_5562af73.HTM?jumpto=view_welcomead_1407269622719

Figures

Grahic Jump Location
Fig. 1

Substrate subjected to an embedded localized constant heat source of finite length Wg, and a constant substrate base temperature. The remaining surfaces are assumed adiabatic.

Grahic Jump Location
Fig. 2

Line heat source of finite length l in a semi-infinite solid

Grahic Jump Location
Fig. 3

Schematic cross section of a PA MMIC package and the thermal resistance network

Grahic Jump Location
Fig. 4

Details of the 3D finite element mesh: (a) in the carrier and jig and (b) around the gates

Grahic Jump Location
Fig. 5

A typical temperature distribution at the base of a substrate of a packaged PA MMIC computed from FEA and fitted with a Lorentz function

Grahic Jump Location
Fig. 6

Values of TL for varying ls and λ, with b = 100 μm

Grahic Jump Location
Fig. 7

Determination of w from thickness of substrate, b, length of heat source, ls, and angle β

Grahic Jump Location
Fig. 8

Effect of ls and β on To,max for λ = 0.5 W/mm

Grahic Jump Location
Fig. 9

Effect of ls and β on To,max for λ = 1.0 W/mm

Grahic Jump Location
Fig. 10

Effect of ls and β on To,max for λ = 1.5 W/mm

Grahic Jump Location
Fig. 11

Effect of ls and β on To,max for λ = 2.0 W/mm

Grahic Jump Location
Fig. 12

Variation of βo with ls

Grahic Jump Location
Fig. 13

Comparison between present analytical method, Darwish et al. [12], FEA, and TRT-measured temperatures for the PA MMIC

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In