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Research Papers

Effect of Through-Silicon-Via Joule Heating on Device Performance for Low-Powered Mobile Applications

[+] Author and Article Information
Fahad Mirza

Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street,
Woolf Hall Mechanical Engineering, Room 211,
Arlington, TX 76019
e-mail: fmirza@mavs.uta.edu

Gaurang Naware

Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street,
Woolf Hall Mechanical Engineering, Room 211,
Arlington, TX 76019
e-mail: gaurang.naware@mavs.uta.edu

Ankur Jain

Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street,
Engineering Lab Building, Room 203,
Arlington, TX 76019
e-mail: jaina@uta.edu

Dereje Agonafer

Mechanical and Aerospace Engineering,
University of Texas at Arlington,
500 W First Street,
Woolf Hall Mechanical Engineering, Room 211,
Arlington, TX 76019
e-mail: agonafer@uta.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received October 22, 2013; final manuscript received July 17, 2014; published online September 19, 2014. Assoc. Editor: Ashish Gupta.

J. Electron. Packag 136(4), 041008 (Sep 19, 2014) (7 pages) Paper No: EP-13-1122; doi: 10.1115/1.4028076 History: Received October 22, 2013; Revised July 17, 2014

Three-dimensional (3D) through-silicon-via (TSV) technology is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. TSVs provide high speed signal propagation due to reduced interconnect lengths as compared to wire-bonding. The current flowing through the TSVs results in localized heat generation (joule heating), which could be detrimental to the device performance. The effect of joule heating on performance measured by transconductance, electron mobility (e mobility), and channel thermal noise is presented. Results indicate that joule heating has a significant effect on the junction temperature and subsequently results in 10–15% performance hit.

Copyright © 2014 by ASME
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References

Figures

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Fig. 1

ITRI 3D IC roadmap [2]

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Fig. 2

Comparison between 2D and 3D packages [16]

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Fig. 3

Variation of e and hole mobility with doping concentration (cm−3) [14]

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Fig. 4

Variation of e and hole mobility with temperature at different doping concentrations (top curve: 1016, 1017; bottom: 1018 cm−3) [14]

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Fig. 5

Variation of resistivity with temperature [20]

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Fig. 6

Quarter symmetry model showing symmetry faces

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Fig. 7

Model cross section

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Fig. 8

Meshed model (global)

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Fig. 9

Meshed TSV (global)

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Fig. 10

Submodel—2 × 2 TSVs (detailed geometry)

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Fig. 11

Temperature distribution—package (no TSV current)

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Fig. 12

Temperature distribution—bottom die (no TSV current)

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Fig. 13

Temperature distribution—bottom die (40 mA TSV current)

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Fig. 14

Temperature distribution—bottom die with TSVs (40 mA TSV current)

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Fig. 15

Maximum temperature for various chip power—global model

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Fig. 16

Meshed global and submodel

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Fig. 17

Temperature distribution—comparison between global and submodel response (no TSV current)

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Fig. 18

Temperature distribution—comparison between global and submodel response (40 mA TSV current)

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Fig. 19

Variation in performance with TSV joule heating for 4 W total power

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Fig. 20

Variation in performance hit with chip power for 40 mA case (normalized to the baseline case)

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Fig. 21

Variation of e mobility with TSV thermal conductivity

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Fig. 22

Variation of device transconductance with TSV thermal conductivity (at different joule heating scenarios)

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Fig. 23

Variation of channel noise with TSV thermal conductivity (at different joule heating conditions)

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