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Research Papers

Void Detection in Dielectric Films Using a Floating Network of Substrate-Embedded Electrodes

[+] Author and Article Information
Stephen H. Taylor

Cooling Technologies Research Center,
An NSF I/UCRC,
School of Mechanical Engineering,
Purdue University,
West Lafayette, IN 47907

Suresh V. Garimella

Cooling Technologies Research Center,
An NSF I/UCRC,
School of Mechanical Engineering,
Purdue University,
West Lafayette, IN 47907
e-mail: sureshg@purdue.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received October 6, 2013; final manuscript received July 18, 2014; published online September 19, 2014. Assoc. Editor: Ashish Gupta.

J. Electron. Packag 136(4), 041007 (Sep 19, 2014) (11 pages) Paper No: EP-13-1115; doi: 10.1115/1.4028075 History: Received October 06, 2013; Revised July 18, 2014

A sensor is developed for simple, in situ characterization of dielectric thermal interface materials (TIMs) at bond line thicknesses less than 100 μm. The working principle is based on the detection of regions of contrasting electric permittivity. An array of long, parallel electrodes is flush-mounted into each opposing substrate face of a narrow gap interface, and exposed to the gap formed between the two surfaces. Electrodes are oriented such that their lengthwise dimension in one substrate runs perpendicular to those in the other. A capacitance measurement taken between opposing electrodes is used to characterize the interface region in the vicinity of their crossing point (junction). The electric field associated with each electrode junction is numerically simulated and analyzed. Criteria are developed for the design of electrode junction geometries that localize the electric fields. The capacitances between floating-ground electrodes in the electrode sensor configuration employed give rise to a nontrivial network of interacting capacitances which strongly influence the measured response at any junction. A generalized solution for analyzing the floating network response is presented. The technique is used to experimentally detect thermal grease spots of 0.2 mm to 1.8 mm diameter within a 25 μm interface gap. It is necessary to use the generalized solution to the capacitance network developed in this work to properly delineate regions of contrasting permittivity in the interface gap region using capacitance measurements.

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References

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Figures

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Fig. 6

Minimum pitch for parallel electrodes normalized such that a value of 0 corresponds to an electrode pitch equal to the electrode width, and a value of 1 correspond to an electrode pitch equal to the electrode length. The results are shown for several values of electrode length Λ as a function of gap thickness.

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Fig. 5

Plot of dimensionless capacitance versus normalized gap thickness η for several values of normalized electrode length Λ. The behavior of an ideal parallel-plate capacitor of area w × w is shown for comparison.

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Fig. 4

Top: contour plot of electric field on the lower surface of the top electrode. The one-quarter domain is shown corresponding to the shaded region in Fig. 3. Bottom: dependence of capacitance along the electrode length.

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Fig. 3

Top view of domain of interest for sample case (L = 5 mm; H = 0.25 mm; w = 1 mm; pmin = 3.37 mm). The shaded region of the top electrode surface corresponds to the contour plot in Fig. 4.

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Fig. 2

Domain of interest for a single electrode pair, composed of the gap region between two substrates

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Fig. 1

Schematic diagram of proposed device configuration for characterization of dielectric interfaces

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Fig. 10

Experimental test unit with an M = N = 5 electrode array. The two acrylic substrates are shown placed flush together.

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Fig. 7

Schematic diagram of a two-by-two system of electrodes. The desired capacitance measurement junction is shown as a solid black arrow.

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Fig. 8

Circuit network created by an M × N array of electrodes. For the case shown, M = N = 5, h = 2, and k = 4.

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Fig. 9

Layout of the square matrix, A, of dimension MN + M + N, describing the circuit network. The system is shown as a compilation of six submatrices.

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Fig. 11

Comparison of experimental capacitance measurements with predictions from a representative junction simulation and the network model as a function of gap size H

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Fig. 12

Theoretical and experimental results for an empty air gap, H = 25 μm, in fF: (a) network model results, (b) experimental results, and (c) model error

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Fig. 13

Baseline estimate for empty air gap, H = 25 μm in fF: (a) single junction simulation, (b) reverse network model calculation on experimental data providing the calibrated baseline, and (c) model error

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Fig. 14

Photograph of the grease spot for case 2 between the horizontal electrode underneath and vertical electrode above (left) and with top substrate removed (right)

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Fig. 15

Graphic illustration of grease spots used in the experiment, drawn to scale

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Fig. 16

Data analysis steps for Case 1 showing capacitance in fF: (a) experimentally measured values, (b) junction capacitance map obtained by solving the reverse network model using measured values (junction values lower than the baseline values in (b) are highlighted in yellow), and (c) junction capacitance map using the constrained reverse network model. The darkened cell indicates that the junction detection zone contains grease.

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Fig. 17

Capacitance change for the six different grease-spot cases shown in Figure 15 inside a 25 um gap, in fF. Junctions affected by the presence of grease in their detection zones are darkened.

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