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Research Papers

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

[+] Author and Article Information
Yassir Madhour

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland;
IBM Research—Zurich,
Rüschlikon 8803, Switzerland
e-maill: yassir.madhour@epfl.ch

Brian P. d'Entremont

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland
e-mail: brian.dentremont@epfl.ch

Jackson Braz Marcinichen

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland
e-mail: jackson.marcinichen@epfl.ch

Bruno Michel

IBM Research—Zurich,
Rüschlikon 8803, Switzerland
e-mail: bmi@zurich.ibm.com

John Richard Thome

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland
e-mail: john.thome@epfl.ch

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 30, 2013; final manuscript received April 13, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie.

J. Electron. Packag 136(2), 021006 (Apr 29, 2014) (10 pages) Paper No: EP-13-1080; doi: 10.1115/1.4027436 History: Received July 30, 2013; Revised April 13, 2014

Three-dimensional (3D) stacking of integrated-circuit (IC) dies increases system density and package functionality by vertically integrating two or more dies with area-array through-silicon-vias (TSVs). This reduces the length of global interconnects and the signal delay time and allows improvements in energy efficiency. However, the accumulation of heat fluxes and thermal interface resistances is a major limitation of vertically integrated packages. Scalable cooling solutions, such as two-phase interlayer cooling, will be required to extend 3D stacks beyond the most modest numbers of dies. This paper introduces a realistic 3D chip stack along with a simulation method for the heat spreading and flow distribution among the channels of the evaporators. The model includes the significant sensitivity of each channel's friction factor to vapor quality, and hence mass flow to heat flux, which characterizes parallel two-phase flows. Simulation cases explore various placements of hot spots within the stack and effects which are unique to two-phase interlayer cooling. The results show that the effect of hot spots on individual dies can be mitigated by strong interlayer heat conduction if the relative position of the hot spots is selected carefully to result in a heat load and flow which are well balanced laterally.

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Figures

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Fig. 1

CMOSAIC Test Vehicle description–chip stack package with silicon embedded heat transfer structures. (a) Ensemble view of package with all components. (b) Vertical cross section describing the multiple layers and their respective thicknesses.

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Fig. 2

Illustration of the header geometry

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Fig. 3

Discretization scheme of chip stack

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Fig. 4

Block diagram of solution technique

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Fig. 5

Top front view of single 10 × 10 mm2 chip with 3 × 3 hot spot array layout. Microchannels are etched on the back.

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Fig. 6

Illustrations of the various patterns of active heaters applied to studied chip stack package

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Fig. 7

Temperature versus vertical position within the chip stack for Heat Load Pattern 1 at 50 W/cm2 per chip

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Fig. 8

Temperature versus vertical position within the chip stack for Heat load Pattern 2 at 50 W/cm2 per chip

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Fig. 9

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 3 at 38 W/cm2; TSAT = 60 °C

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Fig. 10

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 4 at 24 W/cm2; TSAT = 60 °C

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Fig. 11

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 5 at 50 W/cm2; TSAT = 60 °C

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Fig. 12

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 5 at 82 W/cm2; TSAT = 60 °C

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Fig. 13

Heat flux and heat transfer coefficient versus axial position along the center channel; Heat Load Pattern 5 at 82 W/cm2; TSAT = 60 °C

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Fig. 14

Fluid pressure along the center channel; Heat Load Pattern 5 at 82 W/cm2; TSAT = 60 °C

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Fig. 15

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 4 at 24 W/cm2; TSAT = 30 °C

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