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Research Papers

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks OPEN ACCESS

[+] Author and Article Information
Yassir Madhour

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland;
IBM Research—Zurich,
Rüschlikon 8803, Switzerland
e-maill: yassir.madhour@epfl.ch

Brian P. d'Entremont

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland
e-mail: brian.dentremont@epfl.ch

Jackson Braz Marcinichen

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland
e-mail: jackson.marcinichen@epfl.ch

Bruno Michel

IBM Research—Zurich,
Rüschlikon 8803, Switzerland
e-mail: bmi@zurich.ibm.com

John Richard Thome

Heat and Mass Transfer Laboratory,
Swiss Institute of Technology,
EPFL STI IGM LTCM,
Lausanne CH-1015, Switzerland
e-mail: john.thome@epfl.ch

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 30, 2013; final manuscript received April 13, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie.

J. Electron. Packag 136(2), 021006 (Apr 29, 2014) (10 pages) Paper No: EP-13-1080; doi: 10.1115/1.4027436 History: Received July 30, 2013; Revised April 13, 2014

Three-dimensional (3D) stacking of integrated-circuit (IC) dies increases system density and package functionality by vertically integrating two or more dies with area-array through-silicon-vias (TSVs). This reduces the length of global interconnects and the signal delay time and allows improvements in energy efficiency. However, the accumulation of heat fluxes and thermal interface resistances is a major limitation of vertically integrated packages. Scalable cooling solutions, such as two-phase interlayer cooling, will be required to extend 3D stacks beyond the most modest numbers of dies. This paper introduces a realistic 3D chip stack along with a simulation method for the heat spreading and flow distribution among the channels of the evaporators. The model includes the significant sensitivity of each channel's friction factor to vapor quality, and hence mass flow to heat flux, which characterizes parallel two-phase flows. Simulation cases explore various placements of hot spots within the stack and effects which are unique to two-phase interlayer cooling. The results show that the effect of hot spots on individual dies can be mitigated by strong interlayer heat conduction if the relative position of the hot spots is selected carefully to result in a heat load and flow which are well balanced laterally.

In the semiconductor industry, IC feature sizes have been gradually reduced to integrate more transistors. This trend, as predicted by Moore's Law [1], consists of shrinking the transistor's gate dimensions to allow the reduction of the gate delay and the switching time of an individual transistor, thus decreasing operating voltages, improving electrical performance and, of course, increasing the number of transistors on a single chip. However, the speed of an electrical signal in an IC is also governed by the signal propagation time between transistors, and the performance of the interconnect wires is degraded as technology nodes continue to scale down, since smaller cross section wires have increased resistance and narrower metal pitches due to increased transistor density can raise the capacitance [2].

Remaining in a two dimensional plane and switching to larger system-on-chip (SOC) dies with mixed technology designs does not provide a long term solution, since the integration of different technologies on a single chip would, on top of increasing the die area, require different processes to produce these different functions, which would raise material, fabrication and cost issues. Meanwhile, the form factor of computing systems continues to be reduced for several applications, from servers to handheld devices.

3D stacking of integrated-circuit dies presents itself as an interesting alternative. It increases system density and package functionality by vertically integrating two or more chips. The vertical integration of IC chips using TSVs reduces the length of global interconnects and accordingly the signal delay time, while also improving bandwidth. Furthermore, the shorter communication distances help improve energy efficiency, by reducing power dissipation. Aside from the gain in electrical performance, other drivers such as a decrease in power consumption and noise, a form factor improvement, lower costs and more functionality show the significant benefits of 3D integration.

Efficient heat dissipation in IC packages is crucial to support the packing density and performance scaling of future systems [3,4]. The ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. The demand for higher computational performance results in microchips with an increasing number of cores and amount of cache memory. These cores communicate through long wires which consume significant energy and generate a considerable amount of heat. The International Technology Roadmap for Semiconductors (ITRS) projects that the power density of a single chip package will increase to 108 W/cm2 for cost performance applications in 2018 [5], from the current power density of 60–80 W/cm2. Thus, heat removal has become an ever increasing challenge, and the development of new chip cooling concepts is of utmost importance. Indeed, the reliability, performance, and power dissipation of interconnects and transistors are heavily dependent on their operating temperature. Therefore, back-side microchannel fluidic cooling concepts, be it single-phase water or two-phase dielectric evaporative cooling using environmentally friendly refrigerants, were introduced into high-end server products [6,7].

Single cavity back-side heat removal of micro electronics and power electronics devices using dielectric evaporative fluids (refrigerants) was demonstrated to be an effective and controllable process. Although the application of the two-phase flow cooling strategies introduces different design and modeling challenges compared to single-phase water flow techniques, these are justified by the great increase in heat transfer coefficients provided by two-phase evaporators via the utilization of the refrigerant's latent energy to extract heat. As a result, enhanced thermal performance, better axial temperature uniformity and reduced coolant flow rates, and thus pumping powers [8], are obtained. Therefore, flow boiling heat transfer has been extensively analyzed in order to determine the impact of factors such as heat exchanger design and geometry, fluid properties, flow velocity, saturation temperature, degree of subcooling and many others, on the process itself. Agostini et al. [9] presented a comprehensive state-of-the-art review of high heat flux cooling technologies that include liquid jet impingement, single-phase liquid cooling, and two-phase flow boiling in copper or silicon microstructures. Marcinichen et al. [10] proposed a multimicrochannel two-phase refrigerant evaporation system as a green solution for the cooling of supercomputer blade servers and clusters, which can contain up to 64 blades per rack (56 for 4 blade centers in a normal 2 m rack and 70 for 5 blade centers in a high 2.3 m rack) cabinet, including their respective memory.

However, applying these concepts to the back side of 3D stacks instead of single chips will only be of temporary efficiency, as a major limitation of vertically integrated packages is that heat fluxes and thermal interface resistances accumulate with each layer. Therefore, scalable cooling solutions, such as interlayer cooling, need to be investigated. Several studies have already focused on the fabrication and assembly of such new systems. Dang et al. [11] showed the feasibility of a silicon chip with an embedded microchannel heat sink and novel thermofluidic chip input/output (I/O) interconnects, fabricated using wafer-level and CMOS compatible batch processing, with its extension to a 3D chip stack using TSVs for electrical vertical integration. King et al. [12] reported for the first time the configuration, fabrication, and experimental testing of a 3D integrated system that can support the power delivery, signaling, and heat removal requirements for high performance chips. However focus was directed on fabrication as well as assembly, and no thermal measurements were performed nor presented. Brunschwiler et al. [13] presented an interlayer cooling concept, consisting of a 5-layer chip stack where every chip is connected individually via wire-bonding. A hot-spot aware heat transfer study was performed with water as working fluid. The authors identified that microchannels efficiently mitigated hot spots by distributing the dissipated heat to multiple cavities due to their low porosity and that pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. The authors concluded that large stacks of 4 cm2 can be cooled sufficiently with a 4-port fluid delivery architecture, which improves the flow rate four times compared to the 2-port version. Most recently, Szczukiewicz et al. [14,15] have presented test results for a 67 channel-microevaporator with 100 × 100 μm2 silicon channels at heat fluxes approaching 50 W/cm2. These 2D tests were conducted as a test case for 3D stacks with the same channel dimensions.

The present paper focuses on two-phase evaporative cooling inside 3D chip stack systems. A realistic concept is presented, and a thermal modeling method is defined and applied to that design. Since experimental results for flow boiling of refrigerants inside multicavity systems do not exist yet, a prediction tool, built from pre-existing and proven prediction methods for channels of the 100 μm size range, is needed to help guide the future first experimental campaigns. This paper presents the implementation of such a model and investigates the effects of heat load placement inside a chip stack in order to improve the heat and flow spreading.

Intra Chip Stack Thermal Management.

This paper presents simulation results, corresponding to an actual test vehicle, on which technical development and fabrication are ongoing and which has not yet been tested. Figures 1(a) and 1(b) show the concept for an intrachip stack thermal management system, developed for the CMOS advanced interlayer cooling consortium (CMOSAIC), whose principal aim is to investigate heat transfer effects in such systems using water as well as refrigerant cooling. The purpose of this particular test vehicle is to demonstrate the feasibility of intra chip stack fluidic cooling via two-phase evaporative heat transfer.

The package consists of a chip stack attached to a larger silicon interposer, as shown in Fig. 1(a), acting as an intermediate between PCB1 and the stack. The interposer is glued and wedge-wedge wire-bonded to the PCB1 using 25 μm-thick aluminum wires. The electrical connection from PCB1 to PCB2 is done via an LGA/BGA socket system. The socket, with the PCB1 plugged inside, is C4 bonded to the PCB2 prior to the application of underfill. External wires/connectors on PCB2 (not shown in Fig. 1(a)) are used to connect the package to a power supply. A stainless steel frame is coupled with the socket to ensure proper electrical contact.

Five 380 μm-thick 10 × 10 mm2 silicon chips (LV1 to 5, see Figs. 1(a) and 1(b)) are flip-chip bonded to form the chip stack, as shown in Fig. 1(a). These chips have been double-side micro-processed at wafer-level and represent mock-ups of real devices, with controlled heaters acting as cores and embedded microchannels on the back for integrated cooling.

First, copper TSVs are etched through the silicon and filled, with a diameter of 64 μm per TSV (for LV1 to 5). The TSVs are electrically insulated with a 1.5 μm silicon dioxide liner that is oven-grown right after via etching. Copper filling is done via double-sided electroplating. On the front side of the wafer, the (aluminum) heaters are deposited via sputter deposition (250 nm) directly on top and around the open vias (for LV1 to 5), some of these connecting the pads for the heaters at each level. The under bump metallization (UBM, 2 μm nickel plus 500 nm gold) is then sequentially deposited on the same side via sputtering on top of the still open vias (for LV1 to 4), to allow the flip-chip bonding of the superior chip.

On the back side of the wafer, solder interconnects with their respective UBM pads are electroplated (2 μm nickel, 1 μm gold, 15 μm eutectic silver tin) for the bonding to the inferior chip (for LV1 to 5). Additionally fifty 100 × 100 μm microchannels are etched on the back side of each chip (for LV2 to 5) via a deep reactive ion etching (DRIE) process, thus forming the multiple evaporator layers where flow boiling will occur (E1 to E4 in Fig. 1(b)).

After formation of the chip stack via flip-chip bonding of the LV1 to LV5 chips, underfill is applied between the stack and the interposer chip (Fig. 1(b)).

Finally, to supply coolant fluid, a manifold made of several parts is fitted over the chip stack. It is omitted for clarity in Fig. 1 and illustrated separately in Fig. 2. Fluid enters through an inlet tube, flows down through the inlet header, turns 90 deg into the individual channels of the chip stack, and then exits up the outlet header and into the outlet tube.

Simulation Method.

The thermal simulations were carried out with the latest version of LTCM's in-house microchannel evaporator code [16] which has been recently modified to accommodate the arbitrary placement of multiple evaporator layers (E1 to E4) and heating layers (LV1 to LV5) within a single microelectronic package. The code iteratively considers 3D heat conduction in the solid materials of the microelectronic package (Table 1) via finite difference solution (Fig. 3) followed by heat transfer and pressure drop in the channels using experimentally validated correlations and models. The objective is a steady-state solution for heat and fluid flow which satisfies both thermal considerations and the requirement that each channel—as connected between two shared fluid headers—must have equal pressure drop. Since frictional pressure drop is a strong function of void fraction, the heat and fluid flow are strongly coupled, which unfortunately results in the channels most heavily loaded with heat receiving the least amount of flow.

LTCM's microchannel code is implemented in MATLAB with fluid properties obtained from the NIST REFPROP (version 8.0) software library. The loop of iteration is depicted by the block diagram in Fig. 4.

In modeling, the chip at the macro scale (i.e., accounting for but not resolving the TSVs), the chip was considered as a homogenous yet anisotropic composite of two isotropic materials. Expressions from Tavman [17] represent the bulk conductivity of a composite consisting of circular fibers spaced regularly on a rectangular array. The conductivity in the vertical direction, along the TSVs, is quite intuitively, an average of that of copper (Cu) and silicon (Si), weighted by the volume fraction of copper.Display Formula

(1)kV=kSi+(kCu+kSi)FCu

The conductivity in the horizontal direction, across the TSVs, isDisplay Formula

(2)kH=kSi(1+2FCukCu+kSikCu-kSi-FCu+kCu-kSikCu+kSi(0.30584FCu4+0.013363FCu8))

The heat conduction equation is thusDisplay Formula

(3)ddz(kHdTdx)+ddz(kHdTdy)+ddz(kVdTdz)=0

with adiabatic boundary conditions applied at all edges of the domain. Where the domain is bisected by the evaporators, boundary conditions at the top (t) and bottom (b) of the evaporator come directly from energy balance with Tf being the fluid temperatureDisplay Formula

(4)Lfh+LcwLfw+Lcwηα(Tt-Tf)convection+LfwLfw+LcwkALfh(Tt-Tb)cond.throughfins=kAdTtdzchipcond.+heater(where present)qt,elec
Display Formula
(5)Lfh+LcwLfw+Lcwηα(Tb-Tf)+LfwLfw+LcwkALfh(Tb-Tt)=-kAdTbdz+qb,elec".

The fin efficiency for the two-ended fin, η, including the finite contact resistance at each end of the fin, has been derived asDisplay Formula

(6)η=(Tt+Tb)(cosh(mL)-1)+mk(Rt"Tb+Rb"Tt)sinh(mL)km2(Rt"+Rb")cosh(mL)+m(k2m2Rt"Rb"-1)sinh(mL)

whereDisplay Formula

(7)m=2αkLfw

η represents, for the dual ended fin, the ratio of the total convective heat rate to a perfect fin in which temperature varies linearly from Tt to Tb. Notably, for the two-ended fin, the convective heat rate is not equal to the rate at either end.

The results of the conduction solution can be used to find the enthalpy in each channelDisplay Formula

(8)dhdz=ηα(Lfh+Lcw)(Tt+Tb-2Tf)GLcwLfh

where the numerator is the convective heat rate per unit length and the denominator is the mass flow rate. Meanwhile, pressure drop is solved according to a correlation (function f) which includes both frictional and momentum pressure dropDisplay Formula

(9)dPdx=f(h,P,G,fluid,goem.)

Equations (8) and (9) are solved for boundary conditions h(z = 0)hi and P(z = 0) = Pi − ΔPIN, where hi and Pi represent the imposed inlet condition. Any appropriate correlation may be used for α and dP/dx. The ones used in this study are described as follows.

Heat Transfer Coefficient.

A new flow pattern-based method [1] uses the Three Zone Model of Thome et al. [18] for the intermittent flow regime and the model of Cioncolini and Thome [19] for the annular flow region (AF). The intermittent flow regime combines the isolated bubble flow (IB) and the coalescing bubble flow (CB) regimes into one. The remaining regime transition (CB-AF) was predicted using a new macro-microscale flow pattern map [20] that can be applied to both the smaller end of macroscale flows and the larger end of microscale flows. This method was recently proven by Szczukiewicz et al. [14] to work well for this fluid and channel size.

Pressure Drop.

A correlating approach [21], based on the vapor core Weber number, was developed from macroscale data, yet it has been extended to cover microscale conditions, resulting in a unified method for predicting annular flows covering both laminar and turbulent liquid films. The correlation proved accurate for the high aspect ratio channels down to 85 μm width in multimicrochannel experiments of Costa-Patry et al. [22] and the 100 × 100 μm2 channels of Szczukiewicz et al [14]. An update of the correlation proposed by Cioncolini et al. [21] was used to consider flows of lower vapor qualities (IB and CB) and also microchannel inlet and outlet restrictions pressure drops, as proposed by Costa-Patry et al. [23]. The pressure loss at the inlet of each channel, PIN, was calculated from single phase flow correlations [24] for an abrupt cross sectional area change from the header (i.e., 1 mm × 10 mm) to the channels (200 × 100 μm × 100 μm) added to that of the 90 deg bend. Also, the pressure drop at the outlet was estimated by an empirical correlation for microchannel evaporators [25], stating thatDisplay Formula

(10)ΔPOUT=G2χρv(LcwLhw)0.2274

The model assumes that the pressure is uniform across the inlet and outlet headers and considers only the inlet/outlet effects, frictional pressure drop in the channel, and acceleration pressure drop to control the flow distribution.

Critical Heat Flux (CHF).

Critical heat flux is estimated via a correlation by Ong and Thome [26]. This is based on the modification of a previous correlation by Wojtan et al. [27], which was ultimately proposed as a microscale variant of the Katto–Ohno correlation [28]. The method is also based on the silicon multi-microchannel evaporator experimental data of Agostini et al. for channels down to 223 μm in width [29-31]. CHF is important to determining whether the converged solution is physically viable. Operation in excess of CHF risks severe thermal damage.

Studied Heat Load Patterns.

The present simulation study focuses on the effect of hot spot patterns rather than the parametric design of the evaporators or of the package as a whole. Thus the geometry has been constrained to the design previously described, supplied with saturated R236fa at 60 °C (see Table 2) at an average mass flux of 2300 kg/m2s for all cases. These parameters were selected to represent the removal of high heat fluxes at temperatures suitable for heat recovery applications. However, an inlet condition of 30 °C is also briefly considered at the end of the paper, decreasing the working fluid pressure and thus ensuring the mechanical integrity of the previously described package for future experimental studies.

Heat was applied in different patterns, all corresponding to variations of a 3 by 3 array (Fig. 5) of equally sized and equally spaced hot spot heaters (HS) on each of the 4 active layers (LV1 to 4, see Figs. 1(b) and 6). Based on a desired maximum outlet vapor quality of 33% for the simultaneous heat/two-phase flow spreading situation, the nominal heat flux was chosen to be 50 W/cm2. Previous experiments in 2D configurations (one evaporator only) with the same channel size have shown that this level of heat flux can be safely supported [15].

First, as a baseline case, all heaters on all four layers (LV1 to LV4) were activated at 50 W/cm2 for a total of 200 W within the chip stack (Heat Load Pattern 1, Fig. 6(a)). Secondly, each heating layer was activated independently at 50 W/cm2 per HS, including an additional case with a fifth layer at the extreme top of the chip stack. The latter case being the worst case scenario, it is presented as Heat Load Pattern 2 (Fig. 6(b)). Next, beginning the study of parallel-to-flow hot spots, only heaters in the center column (see Fig. 5, i.e., three heaters consecutively along the flow direction) were activated (Heat Load Pattern 3, Fig. 6(c)). Then, only heaters in the left column were activated (Heat Load Pattern 4, Fig. 6(d)). For symmetry reasons, the right column was not separately studied. Finally, Heat Load Pattern 5 (Fig. 6(e)) activated columns in a staggered fashion (i.e., HS columns 2,1,3,2, see Fig. 5, on layers LV1 through 4 of the stack, respectively). In this case, the application of heat to each individual chip matches one of the previously tested configurations, but the overall distribution of heat across the package is substantially more uniform.

In a second phase of the study, results for each of these patterns were simulated for various heat fluxes at 2 W/cm2 increments, in order to determine the maximum heat flux that can be sustained without exceeding 33% vapor quality at the exit of any channel.

A similar study was conducted for perpendicular-to-flow hot spots, in which all channels were heated, but over only a third of their length. The first row (i.e., closest to the inlet) was activated (Heat Load Pattern 6), then the second (Heat Load Pattern 7), and finally the third (Heat Load Pattern 8). After that the heat load was staggered across HS rows 2,1,3,2 (Heat Load Pattern 9, Fig. 6(f)) on layers LV1 through 4 of the stack, respectively.

Uniform Heating—All Heaters on at the Chip Level.

Results of the simulations show a strong effect of thermal spreading between the layers, which is effective in attenuating nonuniform heating within the chip stack. However, for the nominal full power case (Heat Load Pattern 1, at 50 W/cm2 per HS and per chip), there is an interesting gradient of temperature through the stack thickness, as shown in Fig. 6. The plot shows the distribution of temperature through the thickness of the stack (dimension Z, see Fig. 1(b)) at several axial locations along the flow direction (i.e., the channel inlet, channel outlet, and center points of each of the three heating elements at 1/6, 1/2, and 5/6 of the channel length, respectively), for the middle channels. The vertical lines on the graph delineate the top and bottom of the 100 μm-tall silicon fins which form each evaporator layer. The temperature distribution is uniform laterally (thus not shown). The axial variation on the graph (i.e., difference between the curves) is due to the changes in fluid temperature and in heat transfer coefficient with increasing vapor quality along the channel. The temperature ultimately decreases toward the channel exit due to the pressure drop in the saturated mixture. The gradient of temperature was not anticipated but can easily be explained. For Heat Load Pattern 1, if the chips were thermally insulated from each other, the conditions at each chip would be identical, resulting in identical temperature gradients to the other chips. Despite having all heaters on all chips, stacking the chips with the hot side of one chip bonded to the cold end of the fins on the next necessarily alters the distribution of heat amongst the layers. Since the chips are of small thermal resistance relative to the convective heat transfer resistance at the channels, the heat load of the upper three heated layers (LV2 to LV4) is effectively shared among the four evaporator layers between which they are situated (E1 to E4), and the LV1 heated layer biases the stack towards higher temperatures and heat load at the bottom, as illustrated by Fig. 7 and Table 3.

Strong interlayer heat spreading is exhibited when only one heater layer is activated and is, in this context, a favorable aspect for the chip designer. Figure 8 and Table 4 show results for Heat Load Pattern 2 (all heat at the top of the stack, Fig. 6(b)) at 50 W/cm2 per HS and per chip, which results in the temperature distribution being skewed and heat conduction being directed downwards in the stack. Thus, only 32% of the heat is removed by the top evaporator layer E4, with the rest passing through the fins of this evaporator into the rest of the stack below. However, reduction in coolant flow in the most heavily heated channels means that CHF is reduced where the heat flux is highest and that variations of outlet vapor quality are accentuated.

Parallel-to-Flow (Column) Hot Spots.

The study of parallel-to-flow hot spots (activation of a column of heaters in the flow direction, see Fig. 5) reveals strong effects of the HS placement on the mass flow distribution widthwise through the evaporator and substantial benefits in distributing hot spots in different locations on different chips in the stack. Figure 9 shows the mass flux distribution across all channels for each layer, which results from shutting down the left and right portions of each chip and leaving the center third of each chip active (Heat Load Pattern 3, Fig. 6(c)). A depression of mass flow is apparent in the center. As a result, the maximum safe heat flux is reduced compared to the case where all heaters were active (Heat Load Pattern 1). Figure 9 shows results for a heat flux of 38 W/cm2 per HS. The maximum outlet vapor quality is 32.5% and comparable to the fully active chip at 50 W/cm2. Moving this column of heat from the center to the left of the chip (Heat Load Pattern 4, Fig. 6(d)) results in fewer lateral spreading, and further reduces the allowable heat flux.

Figure 10 shows the mass flow distribution for this pattern at 24 W/cm2, which results in a maximum outlet vapor quality of 31.9%. At heat fluxes above 44 W/cm2 per HS, the left-most channel is predicted to completely dry out (i.e., achieve quality of one). This is extremely significant to the chip designer, since it suggests that a chip properly designed to handle 50 W/cm2 on all heaters, with a large margin of safety, would start overheating if two thirds of the chip are shut down leaving only the left side active, in the flow direction. The acceptable heat flux (with less than 33% outlet quality) is thus reduced by 52% relative to the baseline case.

Staggering the hot spots on different columns in the direction of the flow, for different layers, results in a more uniform mass flow distribution. Such results (Heat Load Pattern 5, Fig. 6(e)) are shown in Fig. 11. Since it is not possible to evenly distribute the load on the three heater columns over the four chips (LV1 to 4), there is still double the total heat load on the center channels compared to the sides, which is the reason for the apparent depression of mass flow in the center channels on each layer. At 50 W/cm2 in the staggered pattern, the maximum outlet vapor quality is only 17.6%. Heat flux can be increased to 82 W/cm2 per HS for a maximum outlet vapor quality of 33%. Notably, the flow distribution shown in Fig. 12 is only slightly different than the one seen in Fig. 11, indicating that this increase in heat flux for the same heating pattern has a relatively small effect on the mass flow distribution.

Heat transfer coefficient, heat flux, and pressure drop numbers are depicted in Figs. 13 and 14, corresponding to the middle channel (channel 25 out 50) for the same simulation case as the one presented in Fig. 12 (Heat Load Pattern 5, 82 W/cm2 per HS). The overall trend of the heat transfer coefficient (Fig. 13) is a result of the two-phase flow development with increasing vapor quality along the channel. Heat transfer coefficients are low at the very beginning of the channel, where the fluid arrives as a single-phase saturated liquid. The heat transfer coefficient then rises dramatically with the beginning of the isolated bubble regime. Between 2 mm and 3 mm along the channel the residence time of the isolated bubbles is smaller, the average thickness of the films surrounding them is thus thicker, and the heat transfer coefficient lowers. Beyond 3 mm, the flow is in the annular regime and the heat transfer coefficient increases as the annular film gets thinner.

Heat is concentrated within the zones of high heat transfer coefficient, and as illustrated in Fig. 13, the heat flux follows the trend established by the heat transfer coefficient. In Fig. 13, evaporators E1 and E4 show higher heat transfer on the center channel than E2 and E3 since, for Heat Load Pattern 5 (Fig. 6(e)), these are nearest to the heaters which are activated in the center section. The higher heat flux is responsible for the higher maximum heat transfer coefficient in nucleate boiling. The higher heat flux and lower mass flow rate are jointly responsible for the higher vapor quality and earlier transition to annular flow. Additionally, since the total channel wall area (400 μm single channel perimeter × 10 mm channel length × 50 channels) for one evaporator layer is twice the chip footprint area (10 × 10 mm2), a HS heat flux of 82 W/cm2 nominally corresponds to a channel wall heat flux of 41 W/cm2. Actual average heat fluxes on the middle channel are lower than this due to lateral and vertical spreading into unheated zones.

Numbers for thermal resistance, over the total 10 mm × 10 mm area of the chip stack, put the relative contributions into perspective. The total thermal resistance for conduction from the top to bottom of the four heated chips is 0.135 K/W. Of this 0.012 K/W is contributed by the 280 μm thick base of each chip, 0.017 K/W is contributed by the conduction through the fins of each evaporator, and 0.004 K/W is contributed by the solder connection at the bottom of each evaporator to the next chip. By comparison, selecting a heat transfer coefficient of 35000 W/m2K (from Fig. 13) as representative, the thermal resistance to convection is 0.286 K/W. Thus, the resistance to heat convection into a single micro evaporator is roughly twice that of the entire chip stack.

Given that the manifold inlet pressures have been constrained to be equal, pressure profiles along the channels are essentially indistinguishable, as shown in Fig. 14. The pressure drop associated with the flow of single phase liquid from the inlet manifold to the entrance of the channels is small, but the one associated with the two-phase flow mixture exiting the manifold is significant.

Table 5 summarizes the strong advantage of the staggered configuration of hot spots on the various chips. The allowable heat flux, within acceptable bounds of outlet vapor quality, is increased more than three-fold relative to the left-side only pattern (Heat Load Pattern 4, Fig. 6(d)), even though the total active heated area is the same within the stack.

Perpendicular to Flow (Row) Hot Spots.

The study of the placement of perpendicular-to-flow hot spots, occupying a full row of the heater array across the width of the chip (see Fig. 5), is summarized in Table 6 and shows that staggering hot spots reduces peak temperatures.

In these cases, the heat load is always uniform across the width of the evaporator, so there is no lateral flow imbalance, since all the channels experience the same heat load. Outlet vapor qualities are also small and pose little concern, since only a third of each channel is heated. For Heat Load Patterns 6, 7, and 8 the positioning of hot spots is the same on each layer within the stack (see Table 6) and thus there is only a small flow imbalance between the evaporator layers. This means that in this perpendicular configuration, actually staggering the hot spots very slightly increases the flow imbalance, evidenced in the reported vapor quality numbers in Table 6 for Heat Load Pattern 9 (Fig. 6(f)), compared to the previous three patterns. However, the peak heat flux incident on the channel wall is considerably reduced, resulting in a reduction in peak junction temperature for the staggered case.

Effect of Saturation Temperature.

Repeating the same pattern and intensity of heat shown in Fig. 10 (Heat Load Pattern 4 at 24 W/cm2 per HS), but this time with the fluid inlet saturation temperature reduced to 30 °C, slightly increases the flow imbalance while also decreasing the maximum outlet vapor quality. This mass flow distribution is shown in Fig. 15. Table 7 compares the new results to the ones previously presented at 60 °C in Fig. 10. The flow imbalance is increased due to the lower refrigerant vapor density at 30 °C and thus larger volumetric generation of vapor (i.e., 153 mm2 J1 at 30 °C versus 82 mm2 J1). However, this happened at lower outlet vapor qualities due to the higher latent heat of vaporization. The stepwise jumps in the right portion of Fig. 15 are due to the laminar-turbulent transition in the liquid flow used in the Lockhart–Martinelli portion of the Cioncolini model [22]. These are evident at 30 °C and not at 60 °C due to the differences in liquid viscosity (see Table 2).

General Discussion.

The strong stack conductance due to the low chip thermal resistances compared to the convection from solid to fluid promotes good heat load sharing amongst the evaporator layers. The implication is that in multi-evaporator scenarios with hot spots, there may exist an optimum heat transfer coefficient relative to the conductance of the surrounding layers, which is sufficiently large to allow the conveyance of heat from the wall to the microchannel, but not so large that the channel closest to the hot spot absorbs an excessive share of the heat load causing channel dryout or excessive outlet vapor quality. Additionally, strong intrastack conductance relative to convection from the fins was observed to result in the steplike temperature profile through the thickness of the chip, shown in Fig. 7, which is not a favorable effect for temperature uniformity. Notably, under uniform and nonuniform heat loads, both of these aspects would discourage the use of large aspect ratio fins, which increase the effect of convection while decreasing interlayer conductance.

A further issue is that the thermal consequence of dryout and CHF may require substantial rethinking in the context of such microevaporator designs. In the traditional context of single layer (2D) heat flux-controlled microevaporators, these are considered do-not-exceed limits. Thus there has in the past been little incentive to study postdryout heat transfer or consider it as a viable regime for operation. In the context of the multi-evaporator chip stack this concept is considerably altered, since excursions of the channel wall temperature are limited by the effect of conduction to adjacent layers.

A realistic concept for a 3D chip stack with integrated cooling has been presented along with simulation results, showing the sensitivity of the two-phase flow to the arrangement of hot spots among the layers. The model combines a finite difference solution to the 3D heat conduction in the solid materials with heat transfer and pressure drop in embedded microchannels, using existing, experimentally validated correlations and models.

The strong intrastack conductance compared to the convection from solid to fluid was well illustrated in the case where only the top most chip in the stack (LV5) was heated, which resulted in only 32% of the heat removed by the closest evaporator (E4), with the rest passing through the fins into the rest of the stack below.

The importance of intrastack heat spreading and the need for a holistic design of all thermal loads and all evaporators are illustrated by contrasting heat flux required in each of the following cases to obtain the same maximum outlet quality of 33%:

  • 50 W/cm2 applied uniformly to each of the four heaters (Heat Load Pattern 1), for a total of 200 W to the package

  • 38 W/cm2 applied to only the center third laterally (Pattern 3) for a total of 50.7 W to the package

  • 24 W/cm2 applied to one lateral third of the chip (Pattern 4) for a total of 32.0 W

  • 82 W/cm2 staggered such that two chips are active in the center third and one on each lateral edge (Pattern 5), for a total of 109.3 W

Note that the above results show that, in contrast with single phase cooling, shutting down the heat flux on two thirds of the chip reduces the maximum heat flux allowable into the remaining portion due to flow imbalance. Each of the later three cases has the same number of hot spots covering the same shapes and area, so the improvement in allowable heat flux is attributable solely to the effect on the flow in all evaporators of the HS placement on each layer.

For hot spots spanning the width of the chip rather than length, staggering the position is less advantageous. Staggering hot spots along the direction of flow (Pattern 9) increase flow imbalance and slightly increases maximum outlet vapor qualities compared to placing all hot spots in the same sector along the direction of flow (Patterns 6, 7, 8). However, spreading the heat over a large portion of the chip still results in a junction temperature reduction.

The authors would like to thank Gerd Schlottig for his contribution as well as Walter Riess for his continuous support. The CMOSAIC project was scientifically evaluated by SNSF and financed by the Swiss Confederation through the Nano-Tera.ch program.

 

 Nomenclature
  • E =

    evaporator (1 to 4, Fig. 1(b))

  • FCu =

    volume fraction of TSVs (dimensionless)

  • G =

    mass flux (kg m2s1)

  • h =

    specific enthalpy (J/kg)

  • k =

    thermal conductivity (W m1 K1)

  • Lcw =

    channel width (m)

  • Lfh =

    fin height (m)

  • Lfw =

    fin width (m)

  • Lhw =

    header width (m)

  • LV =

    level (1 to 5, chip vertical position in the stack, Fig. 1(b))

  • P =

    pressure (Pa)

  • qelec" =

    metallization layer heat flux (W m2)

  • R" =

    thermal contact resistance (K m2 W1)

  • T =

    temperature (K)

  • x,y,z =

    spatial coordinates (Fig. 2)

  • α =

    heat transfer coefficient (W m2K1)

  • η =

    fin efficiency (dimensionless)

  • χ =

    vapor quality (dimensionless)

Meindl, J. D., Davis, J. A., Zarkesh-Ha, P., Patel, C. S., Martin, K. P., and Kohl, P. A., 2002, “Interconnect Opportunities for Gigascale Integration,” IBM J. Res. Develop., 46(2/3), pp. 245–263. [CrossRef]
Garrou, P., Bower, C., and Ramm, P., 2008, Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits, Vol. 1, Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, Germany, pp. 13–24. [CrossRef]
Sri-Jayantha, S. M., McVicker, G., Bernstein, K., and Knickerbocker, J. U., 2008, “Thermomechanical Modeling of 3D Electronic Packages,” IBM J. Res. Develop., 52(6), pp. 623–634. [CrossRef]
Ruch, P., Brunschwiler, T., Escher, W., Paredes, S., and Michel, B., 2011, “Toward Five-Dimensional Scaling: How Density Improves Efficiency in Future Computers,” IBM J. Res. Develop., 55(5), pp. 15:1–15:13. [CrossRef]
International Technology Roadmap for Semiconductors (ITRS), 2008 Update, available at: http://www.itrs.net/Links/2008ITRS/update/2008_update.pdf
Zimmermann, S., Meijer, I., Tiwari, M. K., Paredes, S., Michel, B., and Poulikakos, D., 2012, “Aquasar: A Hot Water Cooled Data Center With Direct Energy Reuse,” Energy, 43(1), pp. 237–245. [CrossRef]
Madhour, Y., Olivier, J. A., Costa-Patry, E., Paredes, S., Michel, B., and Thome, J. R., 2011, “Flow Boiling of R134a in a Multi-Microchannel Heat Sink With Hotspot Heaters for Energy Efficient Microelectronic CPU Cooling Applications,” IEEE Trans. Compon., Packag. Manuf. Technol., 1(6), pp. 873–883. [CrossRef]
Marcinichen, J. B., Olivier, J. A., and Thome, J. R., 2011, “Reasons to Use Two-Phase Refrigerant Cooling,” Electron. Cooling, 17(1), pp. 22–27.
Agostini, B., Fabbri, M., Park, J. E., Wojtan, L., Thome, J. R., and Michel, B., 2007, “State of The Art of High Heat Flux Cooling Technologies,” Heat Transfer Eng., 28(4), pp. 258–281. [CrossRef]
Marcinichen, J. B., Thome, J. R., and Michel, B., 2010, “Cooling of Microprocessors With Micro-Evaporation: A Novel Two-Phase Cooling Cycle,” Int. J. Refrig., 33(7), pp. 1264–1276. [CrossRef]
Dang, B., Bakir, M. S., Sekar, D. C., King, C. R.Jr., and Meindl, J. D., 2010, “Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips,” IEEE Trans. Adv. Pack., 33(1), pp. 79–87. [CrossRef]
King, C. R.Jr., Sekar, D. C., Bakir, M. S., Dang, B., Pikarsky, J., and Meindl, J. D., 2008, “3D Stacking of Chips With Electrical and Microfluidic I/O Interconnects,” Proceedings of the Electronic Components and Technology Conference (ECTC 2008), Lake Buena Vista, FL, May 27–30. [CrossRef]
Brunschwiler, T., Paredes, S., Drechsler, U., Michel, B., Cesar, W., Leblebici, Y., Wunderle, B., and Reichl, H., 2010, “Heat Removal Performance Scaling of Interlayer Cooled Chip Stacks,” 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Las Vegas, NV, June 2–5. [CrossRef]
Szczukiewicz, S., Borhani, N., and Thome, J. R., 2013, “Two-Phase Heat Transfer and High-Speed Visualization of Refrigerant Flows in 100 × 100 μm2 Silicon Multi-Microchannels,” Int. J. Refrig., 36(2), pp. 402–413. [CrossRef]
Szczukiewicz, S., Borhani, N., and Thome, J. R., 2013, “Two-Phase Flow Operational Maps for Multi-Microchannel Evaporators,” Int. J. Heat Fluid Flow, 42, pp. 176–189. [CrossRef]
Olivier, J. A., Marcinichen, J. B., Bruch, A., and Thome, J. R., 2011, “Green Cooling of High Performance Micro Processors: Parametric Study Between Flow Boiling and Water Cooling,” J. Therm. Sci. Eng. Appl., 3(4), p. 041003. [CrossRef]
Tavman, I. H., 2004, “Thermal Conductivity of Particle Reinforced Polymer Composites,” Nanoengineered Nanofibrous Materials, Kluwer Academic Publishers, Netherlands, pp. 451–459.
Thome, J. R., Dupont, V., and Jacobi, A. M., 2004, “Heat Transfer Model for Evaporation in Microchannels. Part I: Presentation of the Model,” Int. J. Heat Mass Transfer, 47(14–16), pp. 3375–3385. [CrossRef]
Cioncolini, A., and Thome, J. R., 2011, “Algebraic Turbulence Modeling in Adiabatic and Evaporating Annular Two-Phase Flow,” Int. J. Heat Fluid Flow, 32(4), pp. 805–817. [CrossRef]
Ong, C. L., and Thome, J. R., 2011, “Macro-to-Microchannel Transition in Two-Phase Flow: Part 1—Two-Phase Flow Patterns and Film Thickness Measurements,” Exp. Therm. Fluid Sci., 35(1), pp. 37–47. [CrossRef]
Cioncolini, A., Thome, J. R., and Lombardi, C., 2009, “Unified Macro-to-Microscale Method to Predict Two-Phase Frictional Pressure Drops of Annular Flows,” Int. J. Multiphase Flow, 35(12), pp. 1138–1148. [CrossRef]
Costa-Patry, E., Olivier, J. A., Nichita, B. A., Michel, B., and Thome, J. R., 2011, “Two-Phase Flow of Refrigerants in 85 μm-Wide Multi-Microchannels: Part I—Pressure Drop,” Int. J. Heat Fluid Flow, 32(2), pp. 451–463. [CrossRef]
Costa-Patry, E., Olivier, J. A., and Thome, J. R., 2012, “Heat Transfer Characteristics in a Copper Micro-Evaporator and Flow Pattern-Based Prediction Method for Flow Boiling in Microchannels,” Front. Heat Mass Transfer, 3(1), p. 013002. [CrossRef]
Idelchik, I. E., 2005, Handbook of Hydraulic Resistance, 3rd ed., Jaico, Mumbai.
Costa-Patry, E., 2011, “Cooling High Heat Flux Micro-Electronic Systems Using Refrigerants in High Aspect Ratio Multi-Microchannel Evaporators,” Doctoral thesis, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland.
Ong, C. L., and Thome, J. R., 2011, “Macro-to-Microchannel Transition in Two-Phase Flow: Part 2—Flow Boiling Heat Transfer and Critical Heat Flux,” Exp. Therm. Fluid Sci., 35(6), pp. 873–886. [CrossRef]
Wojtan, L., RevellinR., and ThomeJ. R., 2006 “Investigation of Saturated Critical Heat Flux in a Single Uniformly Heated Microchannel,” Exp. Therm. Fluid Sci., 30(8), pp. 765–774. [CrossRef]
Katto, Y., and Ohno, H., 1984, “An Improved Version of the Generalized Correlation of Critical Heat Flux for the Forced Convective Boiling in Uniformly Heated Vertical Tubes,” Int. J. Heat Mass Transfer, 27(9), pp. 1641–1648. [CrossRef]
Agostini, B., Thome, J., Fabbri, M., Michel, B., Caimi, D., and Kloter, U., 2008, “High Heat Flux Flow Boiling in Silicon Multi-Microchannels—Part I: Heat Transfer Characteristics of Refrigerant R236fa,” Int. J. Heat Mass Transfer, 51(21–22), pp. 5400–5414. [CrossRef]
Agostini, B., Thome, J., Fabbri, M., Michel, B., Caimi, D., and Kloter, U., 2008, “High Heat Flux Flow Boiling in Silicon Multi-Microchannels—Part II: Heat Transfer Characteristics of Refrigerant R245fa,” Int. J. Heat Mass Transfer, 51(21–22), pp. 5415–5425. [CrossRef]
Agostini, B., Revellin, R., Thome, J., Fabbri, M., Michel, B., Caimi, D., and Kloter, U., 2008, “High Heat Flux Flow Boiling in Silicon Multi-Microchannels—Part III: Saturated Critical Heat Flux of R236fa and Two-Phase Pressure Drops,” Int. J. Heat Mass Transfer, 51(21–22), pp. 5426–5442. [CrossRef]
Copyright © 2014 by ASME
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References

Meindl, J. D., Davis, J. A., Zarkesh-Ha, P., Patel, C. S., Martin, K. P., and Kohl, P. A., 2002, “Interconnect Opportunities for Gigascale Integration,” IBM J. Res. Develop., 46(2/3), pp. 245–263. [CrossRef]
Garrou, P., Bower, C., and Ramm, P., 2008, Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits, Vol. 1, Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, Germany, pp. 13–24. [CrossRef]
Sri-Jayantha, S. M., McVicker, G., Bernstein, K., and Knickerbocker, J. U., 2008, “Thermomechanical Modeling of 3D Electronic Packages,” IBM J. Res. Develop., 52(6), pp. 623–634. [CrossRef]
Ruch, P., Brunschwiler, T., Escher, W., Paredes, S., and Michel, B., 2011, “Toward Five-Dimensional Scaling: How Density Improves Efficiency in Future Computers,” IBM J. Res. Develop., 55(5), pp. 15:1–15:13. [CrossRef]
International Technology Roadmap for Semiconductors (ITRS), 2008 Update, available at: http://www.itrs.net/Links/2008ITRS/update/2008_update.pdf
Zimmermann, S., Meijer, I., Tiwari, M. K., Paredes, S., Michel, B., and Poulikakos, D., 2012, “Aquasar: A Hot Water Cooled Data Center With Direct Energy Reuse,” Energy, 43(1), pp. 237–245. [CrossRef]
Madhour, Y., Olivier, J. A., Costa-Patry, E., Paredes, S., Michel, B., and Thome, J. R., 2011, “Flow Boiling of R134a in a Multi-Microchannel Heat Sink With Hotspot Heaters for Energy Efficient Microelectronic CPU Cooling Applications,” IEEE Trans. Compon., Packag. Manuf. Technol., 1(6), pp. 873–883. [CrossRef]
Marcinichen, J. B., Olivier, J. A., and Thome, J. R., 2011, “Reasons to Use Two-Phase Refrigerant Cooling,” Electron. Cooling, 17(1), pp. 22–27.
Agostini, B., Fabbri, M., Park, J. E., Wojtan, L., Thome, J. R., and Michel, B., 2007, “State of The Art of High Heat Flux Cooling Technologies,” Heat Transfer Eng., 28(4), pp. 258–281. [CrossRef]
Marcinichen, J. B., Thome, J. R., and Michel, B., 2010, “Cooling of Microprocessors With Micro-Evaporation: A Novel Two-Phase Cooling Cycle,” Int. J. Refrig., 33(7), pp. 1264–1276. [CrossRef]
Dang, B., Bakir, M. S., Sekar, D. C., King, C. R.Jr., and Meindl, J. D., 2010, “Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips,” IEEE Trans. Adv. Pack., 33(1), pp. 79–87. [CrossRef]
King, C. R.Jr., Sekar, D. C., Bakir, M. S., Dang, B., Pikarsky, J., and Meindl, J. D., 2008, “3D Stacking of Chips With Electrical and Microfluidic I/O Interconnects,” Proceedings of the Electronic Components and Technology Conference (ECTC 2008), Lake Buena Vista, FL, May 27–30. [CrossRef]
Brunschwiler, T., Paredes, S., Drechsler, U., Michel, B., Cesar, W., Leblebici, Y., Wunderle, B., and Reichl, H., 2010, “Heat Removal Performance Scaling of Interlayer Cooled Chip Stacks,” 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Las Vegas, NV, June 2–5. [CrossRef]
Szczukiewicz, S., Borhani, N., and Thome, J. R., 2013, “Two-Phase Heat Transfer and High-Speed Visualization of Refrigerant Flows in 100 × 100 μm2 Silicon Multi-Microchannels,” Int. J. Refrig., 36(2), pp. 402–413. [CrossRef]
Szczukiewicz, S., Borhani, N., and Thome, J. R., 2013, “Two-Phase Flow Operational Maps for Multi-Microchannel Evaporators,” Int. J. Heat Fluid Flow, 42, pp. 176–189. [CrossRef]
Olivier, J. A., Marcinichen, J. B., Bruch, A., and Thome, J. R., 2011, “Green Cooling of High Performance Micro Processors: Parametric Study Between Flow Boiling and Water Cooling,” J. Therm. Sci. Eng. Appl., 3(4), p. 041003. [CrossRef]
Tavman, I. H., 2004, “Thermal Conductivity of Particle Reinforced Polymer Composites,” Nanoengineered Nanofibrous Materials, Kluwer Academic Publishers, Netherlands, pp. 451–459.
Thome, J. R., Dupont, V., and Jacobi, A. M., 2004, “Heat Transfer Model for Evaporation in Microchannels. Part I: Presentation of the Model,” Int. J. Heat Mass Transfer, 47(14–16), pp. 3375–3385. [CrossRef]
Cioncolini, A., and Thome, J. R., 2011, “Algebraic Turbulence Modeling in Adiabatic and Evaporating Annular Two-Phase Flow,” Int. J. Heat Fluid Flow, 32(4), pp. 805–817. [CrossRef]
Ong, C. L., and Thome, J. R., 2011, “Macro-to-Microchannel Transition in Two-Phase Flow: Part 1—Two-Phase Flow Patterns and Film Thickness Measurements,” Exp. Therm. Fluid Sci., 35(1), pp. 37–47. [CrossRef]
Cioncolini, A., Thome, J. R., and Lombardi, C., 2009, “Unified Macro-to-Microscale Method to Predict Two-Phase Frictional Pressure Drops of Annular Flows,” Int. J. Multiphase Flow, 35(12), pp. 1138–1148. [CrossRef]
Costa-Patry, E., Olivier, J. A., Nichita, B. A., Michel, B., and Thome, J. R., 2011, “Two-Phase Flow of Refrigerants in 85 μm-Wide Multi-Microchannels: Part I—Pressure Drop,” Int. J. Heat Fluid Flow, 32(2), pp. 451–463. [CrossRef]
Costa-Patry, E., Olivier, J. A., and Thome, J. R., 2012, “Heat Transfer Characteristics in a Copper Micro-Evaporator and Flow Pattern-Based Prediction Method for Flow Boiling in Microchannels,” Front. Heat Mass Transfer, 3(1), p. 013002. [CrossRef]
Idelchik, I. E., 2005, Handbook of Hydraulic Resistance, 3rd ed., Jaico, Mumbai.
Costa-Patry, E., 2011, “Cooling High Heat Flux Micro-Electronic Systems Using Refrigerants in High Aspect Ratio Multi-Microchannel Evaporators,” Doctoral thesis, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland.
Ong, C. L., and Thome, J. R., 2011, “Macro-to-Microchannel Transition in Two-Phase Flow: Part 2—Flow Boiling Heat Transfer and Critical Heat Flux,” Exp. Therm. Fluid Sci., 35(6), pp. 873–886. [CrossRef]
Wojtan, L., RevellinR., and ThomeJ. R., 2006 “Investigation of Saturated Critical Heat Flux in a Single Uniformly Heated Microchannel,” Exp. Therm. Fluid Sci., 30(8), pp. 765–774. [CrossRef]
Katto, Y., and Ohno, H., 1984, “An Improved Version of the Generalized Correlation of Critical Heat Flux for the Forced Convective Boiling in Uniformly Heated Vertical Tubes,” Int. J. Heat Mass Transfer, 27(9), pp. 1641–1648. [CrossRef]
Agostini, B., Thome, J., Fabbri, M., Michel, B., Caimi, D., and Kloter, U., 2008, “High Heat Flux Flow Boiling in Silicon Multi-Microchannels—Part I: Heat Transfer Characteristics of Refrigerant R236fa,” Int. J. Heat Mass Transfer, 51(21–22), pp. 5400–5414. [CrossRef]
Agostini, B., Thome, J., Fabbri, M., Michel, B., Caimi, D., and Kloter, U., 2008, “High Heat Flux Flow Boiling in Silicon Multi-Microchannels—Part II: Heat Transfer Characteristics of Refrigerant R245fa,” Int. J. Heat Mass Transfer, 51(21–22), pp. 5415–5425. [CrossRef]
Agostini, B., Revellin, R., Thome, J., Fabbri, M., Michel, B., Caimi, D., and Kloter, U., 2008, “High Heat Flux Flow Boiling in Silicon Multi-Microchannels—Part III: Saturated Critical Heat Flux of R236fa and Two-Phase Pressure Drops,” Int. J. Heat Mass Transfer, 51(21–22), pp. 5426–5442. [CrossRef]

Figures

Grahic Jump Location
Fig. 1

CMOSAIC Test Vehicle description–chip stack package with silicon embedded heat transfer structures. (a) Ensemble view of package with all components. (b) Vertical cross section describing the multiple layers and their respective thicknesses.

Grahic Jump Location
Fig. 2

Illustration of the header geometry

Grahic Jump Location
Fig. 3

Discretization scheme of chip stack

Grahic Jump Location
Fig. 4

Block diagram of solution technique

Grahic Jump Location
Fig. 5

Top front view of single 10 × 10 mm2 chip with 3 × 3 hot spot array layout. Microchannels are etched on the back.

Grahic Jump Location
Fig. 6

Illustrations of the various patterns of active heaters applied to studied chip stack package

Grahic Jump Location
Fig. 7

Temperature versus vertical position within the chip stack for Heat Load Pattern 1 at 50 W/cm2 per chip

Grahic Jump Location
Fig. 8

Temperature versus vertical position within the chip stack for Heat load Pattern 2 at 50 W/cm2 per chip

Grahic Jump Location
Fig. 9

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 3 at 38 W/cm2; TSAT = 60 °C

Grahic Jump Location
Fig. 10

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 4 at 24 W/cm2; TSAT = 60 °C

Grahic Jump Location
Fig. 11

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 5 at 50 W/cm2; TSAT = 60 °C

Grahic Jump Location
Fig. 12

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 5 at 82 W/cm2; TSAT = 60 °C

Grahic Jump Location
Fig. 13

Heat flux and heat transfer coefficient versus axial position along the center channel; Heat Load Pattern 5 at 82 W/cm2; TSAT = 60 °C

Grahic Jump Location
Fig. 14

Fluid pressure along the center channel; Heat Load Pattern 5 at 82 W/cm2; TSAT = 60 °C

Grahic Jump Location
Fig. 15

Mass flux by channel across each evaporator; 10 × 10 mm2 chip; Heat Load Pattern 4 at 24 W/cm2; TSAT = 30 °C

Tables

Table Grahic Jump Location
Table 1 Chip stack relevant thermal conductivities in W/mK
Table Grahic Jump Location
Table 2 R236fa saturation properties at 30 and 60 °C
Table Grahic Jump Location
Table 3 Results for Heat Load Pattern 1 at 50 W/cm2 per chip
Table Grahic Jump Location
Table 4 Results for Heat Load Pattern 2 at 50 W/cm2 per chip
Table Grahic Jump Location
Table 5 Summary of results for parallel-to-flow hot spots
Table Grahic Jump Location
Table 6 Summary of results for perpendicular-to-flow hot spots
Table Grahic Jump Location
Table 7 Comparison of results for Heat Load Pattern 4 at 24 W/cm2 per HS, for two different fluid inlet temperatures

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