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Technology Review

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

[+] Author and Article Information
Peisheng Liu

Jiangsu Key Laboratory of ASIC Design,
Nantong University,
Nantong 226019, China;
Nantong Fujistu Microelectronics Co., Ltd,
Nantong 226006, China
e-mail: psliu@issp.ac.cn and psliu@ntu.edu.cn

Jinlan Wang

Nantong University,
Nantong 226019, China

Liangyu Tong

Jiangsu Key Laboratory of ASIC Design,
Nantong University,
Nantong 226019, China

Yujuan Tao

Nantong Fujistu Microelectronics Co., Ltd.,
Nantong 226006, China

1Corresponding author.

2Present address: Wu Xi Zhong Wei High-Tech Electronics Co., Ltd., Wuxi 214035, China.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received January 7, 2014; final manuscript received April 6, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie.

J. Electron. Packag 136(2), 024002 (Apr 29, 2014) (7 pages) Paper No: EP-14-1006; doi: 10.1115/1.4027397 History: Received January 07, 2014; Revised April 06, 2014

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

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Figures

Grahic Jump Location
Fig. 1

Cross section of fan-in and fan-out WLP

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Fig. 2

Fabrication process of “chip first” fan-out WLP

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Fig. 3

Fan-out WLP with “RDL first” process [4]

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Fig. 5

Solder bump with RDL

Grahic Jump Location
Fig. 6

WLP with the structure of BOP

Grahic Jump Location
Fig. 7

Solder bumps with polymer collar [7]

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Fig. 8

WLP with copper post under solder bump

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Fig. 9

Different bump shapes with the same pad opening

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Fig. 10

Solder bumps with different core materials: (a) solder bump with copper core and (b) solder bump with polymer core

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Fig. 12

Embedded passives realized with RDL [25]: (a) single-layer spiral inductors and (b) interdigital capacitors

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Fig. 13

Different types of eWLBs [26]: (a) large die size eWLB with one die; (b) eWLB with two dies; and (c) eWLB with three dies

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Fig. 15

Schematic of 3D WLP adopting TSV

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Fig. 16

3D eWLB packaging with TMV for 3D SiP applications [25]

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Fig. 17

MEMS structure adopting WLP technology

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Fig. 18

TSV with copper liner and polymer filling

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