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Technology Review

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

[+] Author and Article Information
Satish G. Kandlikar

Mechanical Engineering Department and
Microsystems Engineering Department,
Rochester Institute of Technology,
Rochester, NY 14623
e-mail: sgkeme@rit.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 30, 2013; final manuscript received February 15, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie.

J. Electron. Packag 136(2), 024001 (Apr 29, 2014) (11 pages) Paper No: EP-13-1081; doi: 10.1115/1.4027175 History: Received July 30, 2013; Revised February 15, 2014

In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 μm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.

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References

Kandlikar, S. G., Kudithipudi, D., and Rubio-Jimenez, C. A., 2011, “Cooling Mechanisms in 3D ICs: Thermo-Mechanical Perspective,” IEEE International Green Computing Conference and Workshops (IGCC), Orlando, FL, July 25–28. [CrossRef]
Tuckerman, D. B., and Pease, R. F., 1981, “High Performance Heat Sinking for VLSI,” IEEE Electron Dev. Lett., 2(5), pp. 126–129. [CrossRef]
Colgan, E. G., Furman, B., Gaynes, M., LaBianca, N., Magerlein, J. H., Polastre, R., Bezama, R., Marston, K., and Schmidt, R., 2007, “High Performance and Subambient Silicon Microchannel Cooling,” ASME J. Heat Transfer, 129(8), pp. 1046–1051. [CrossRef]
Steinke, M. E., and Kandlikar, S. G., 2004, “Single-Phase Liquid Heat Transfer in Plain and Enhanced Microchannels,” ASME 4th International Conference on Nanochannels, Microchannels and Minichannels, Limerick, Ireland, June 19–21, ASME Paper No. ICNMM2006-96227. [CrossRef]
Kandlikar, S. G., and Bapat, A. V., 2007, “Evaluation of Jet Impingement, Spray, and Microchannel Chip Cooling Options for High Heat Flux Removal,” Heat Transfer Eng., 28(11), pp. 911–923. [CrossRef]
Cotler, A. C., Brown, E. R., Dhir, V., and Shaw, M. C., 2004, “Chip-Level Spray Cooling of an LD-MOSFET RF Power Amplifier,” IEEE Trans. Comp. Packag. Technol., 27(2), pp. 411–416. [CrossRef]
Chang, C. J., Chen, H. T., and Gau, C., 2013, “Flow and Heat Transfer of a Microjet Impinging on a Heated Chip: Part I—Micro Free and Impinging Jet,” Nanoscale Microscale Thermophys. Eng., 17(1), pp. 50–68. [CrossRef]
Chang, C. J., Chen, H. T., and Gau, C., 2013, “Flow and Heat Transfer of a Microjet Impinging on a Heated Chip: Part II—Heat Transfer,” Nanoscale Microscale Thermophys. Eng., 17(2), pp. 92–111. [CrossRef]
Kandlikar, S. G., 2012, “History, Advances, and Challenges in Liquid Flow and Flow Boiling Heat Transfer in Microchannels: A Critical Review,” ASME J. Heat Transfer, 134(3), p. 034001. [CrossRef]
Kandlikar, S. G., Colin, S., Peles, Y., Garimella, S., Pease, R. F., Brandner, J. J., and Tuckerman, D. B., “Heat Transfer in Microchannels—2012 Status and Research Needs,” ASME J. Heat Transfer, 135(9), p. 091001. [CrossRef]
Jiang, L., Wong, M., and Zohar, Y., 1999, “Phase Change in Micro-Channel Heat Sinks With Integrated Temperature Sensors,” J. Microelectromech. Syst., 8(4), pp. 358–365. [CrossRef]
Koo, J.-M., Jiang, L., Zhang, L., Zhou, P., Banerjee, S. S., Kenny, T. M., Santiago, J. G., and Goodson, K. E., 2000, “Modeling of Two-Phase Microchannel Heat Sinks for VLSI Chips,” 14th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2001), Interlaken, Switzerland, January 21–25, pp. 422–426. [CrossRef]
Petti, C., Herner, S. B., and Walker, A., “Monolithic 3D Integrated Circuits,” Wafer-Level 3D ICs Process Technology, Springer, New York, Chap. 2. [CrossRef]
Pavlidis, V. F., and Friedman, E. G., 2007, “3-D Topologies for Network-on-Chips,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(10), pp. 1081–1090. [CrossRef]
Wong, S., El-Gamal, A., Griffin, P., Nishio, Y., Pease, F., and Plummer, J., 2007, “Monolithic 3D Integrated Circuits,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA 2007), Hsinchu, Taiwan, April 23–25. [CrossRef]
Lee, K. F., Gibbons, J. F., and Saraswat, K. C., 1979, “Thin Film MOSFETs Fabricated in Laser-Annealed Polycrystalline Silicon,” Appl. Phys. Lett., 35(2), pp. 173–175. [CrossRef]
Geis, M. W., Flanders, D. C., Antoniadis, D. A., and Smith, H. I., 1979, “Crystalline Silicon on Insulators by Graphoepitaxy,” IEDM Technical Digest, IEEE, pp. 210–212.
Akiyana, S., Ogawa, S., Yoneda, M., Yosii, N., and Terui, Y., 1983, “Multilayer CMOS Device Fabricated on Laser Recrystallized Silicon Islands,” 1983 International Electron Devices Meeting, Washington, DC, December, 5–7, Vol. 29, pp. 352–355. [CrossRef]
Kunio, T., Oyama, K., Hayashi, Y., and Morimoto, M., 1989, “Three Dimensional ICs, Having Four Stacked Active Device Layers,” International Electron Devices Meeting (IEDM '89), Washington, DC, December 3–6, pp. 837–890. [CrossRef]
Topol, A. W., LaTulipe, D. C., Shi, L., Frank, D. J., Bernstein, K., Steen, S. E., Kumar, A., Singco, G. U., Young, A. M., Guanini, K. W., and Ieong, M., 2006, “Three-Dimensional Integrated Circuits,” IBM J. Res. Develop., 56(4/5), pp. 491–506. [CrossRef]
Lee, S. B., Tam, S-W., Pefkianakis, I., Lu, S., Chang, F., Guo, C., and Reinman, G., Peng, C., Naik, M., Zhang, L., Cong, J., 2009, “A Scalable Micro Wireless Interconnect Structure for CMPs”, ACM 15th Annual International Conference on Mobile Computing and Networking (MobiCom '09), Beijing, September 20–25, pp. 217–228. [CrossRef]
Shacham, A., Bergmen, K., and Carloni, L. P., 2008, “Photonic Network-on-Chip for Future Generations of Chip Multi-Processors,” IEEE Trans. Comput., 57(9), pp. 1246–1260. [CrossRef]
Davis, W. R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A. M., Steer, M., and Franzon, P. D., 2005, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Des. Test Comput., 22(6), pp. 498–510. [CrossRef]
Koo, J.-M., Im, S., Jiang, L., and Goodson, K. E., 2005, “Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architecture,” ASME J. Heat Transfer, 127(1), pp. 49–58. [CrossRef]
Lu, J.-Q., Devarajan, S., Zeng, A. Y., Rose, K., and Gutmann, R. J., 2005, “Die-on-Wafer and Wafer-Level Three-Dimensional (3D) Integration of Heterogeneous IC Technologies for RF-Microwave-Millimeter Applications,” MRS Proceedings, 833, p. G6.8. [CrossRef]
Pande, P. P., Ganguly, A., Belzar, B., Nojeh, A., and Ivanov, A., 2008, “Novel Interconnect Infrastructures for Massive Multicore Chips—An Overview,” IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, May 18–21, pp. 2777–2780. [CrossRef]
Bakir, M. S., Sekar, D., Thacker, H., and Dang, B., 2008, “3D Heterogeneous Integrated Systems: Liquid Cooling, Power Delivery, and Implementation,” IEEE Custom Integrated Circuits Conference (CICC 2008), San Jose, CA, September 21–24, pp. 663–670. [CrossRef]
Kandlikar, S. G., 2002, “Fundamental Issues Related to Flow Boiling in Minichannels and Microchannels,” Exp. Therm. Fluid Sci., 26(2–4), pp. 389–407. [CrossRef]
Sekar, D. C., King, C., Dang, B., Thacker, H., Joseph, P., Bakir, M., and Meindl, J., 2008, “A 3D-IC Technology With Integrated Microchannel Cooling,” IEEE International Interconnect Technology Conference (IITC 2008), Burlingame, CA, June 1–4, pp. 13–15. [CrossRef]
Dang, B., Bakir, M. S., Sekar, D. C., King, C. R., Jr., and Meindl, J. D., 2010, “Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips,” IEEE Trans. Adv. Packag., 33(1), pp. 79–87. [CrossRef]
Alfieri, F., Tiwari, M. K., Zinovik, I., Poulikakos, D., Brunschwiler, T., and Michel, B., 2010, “3D Integrated Water Cooling of a Composite Multilayer Stack of Chips,” ASME J. Heat Transfer, 132(12), p. 121402. [CrossRef]
Zhang, Y., King, C. R., Zaveri, J., Yoon, J., Sahu, V., Joshi, Y., and Bakir, M. S., 2011, “Coupled Electrical and Thermal 3D IC Centric Microfluidic Heat Sink Design and Technology,” 61st IEEE Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 31–June 3, pp. 2037–2044. [CrossRef]
Zhang, Y., Dembla, A., Joshi, Y., and Bakir, M. S., 2012, “3D Stacked Microfluidic Cooling for High-Performance 3D ICs,” 62nd IEEE Electronic Components and Technology Conference (ECTC), San Diego, CA, May 29–June 1, pp. 1644–1650. [CrossRef]
Zhang, Y., and Bakir, M. S., 2013, “Independent Interlayer Microfluidic Cooling for Heterogeneous 3D IC Applications,” Electron. Lett., 49(6), pp. 404–406. [CrossRef]
Lau, J. H., and Yue, T. G., 2009, “Thermal Management of 3D IC Integration With TSV (Through Silicon Via),” 59th IEEE Electronic Components and Technology Conference (ECTC 2009), San Diego, CA, May 26–29, pp. 635–640. [CrossRef]
Ziabari, A., and Shakouri, A., 2012, “Fast Thermal Simulations of Vertically Integrated Circuits (3D ICs) Including Thermal Vias,” 13th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), San Diego, CA, May 30–June 1, pp. 588–596. [CrossRef]
Shi, B., Srivastava, A., and Bar-Cohen, A., 2012, “Hybrid 3D-IC Cooling System Using Micro-Fluidic Cooling and Thermal TSVs,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, MA, August 19–21, pp. 33–38. [CrossRef]
Sridhar, A., Vincenzi, A., Ruggiero, M., Brunschwiler, T., and Atienza, D., 2010, “Compact Transient Thermal Modeling for 3D ICs With Liquid Cooling Via Enhanced Heat Transfer Cavity Geometries,” 16th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Barcelona, Spain, October, 6–8.
Sridhar, A., Vincenzi, A., Ruggiero, M., Brunschwiler, T., and Atienza, D., 2010, “3D-ICE: Fast Compact Transient Thermal Modeling for 3D ICs With Inter-Tier Liquid Cooling,” Proceedings of the International Conference on Computer-Aided Design, pp. 463–470.
Feng, Z., and Li, P., 2010, “Fast Thermal Analysis on GPU for 3D-ICs With Integrated Microchannel Cooling,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 7–11, pp. 551–555. [CrossRef]
Wilkerson, P., Raman, A., and Turowski, M., 2004, “Fast, Automated Thermal Simulations of Three-Dimensional Integrated Circuits,” 9th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM '04), Las Vegas, NV, June 1–4, pp. 706–713. [CrossRef]
Koo, J.-M., Jiang, L., Zeng, L., Zhou, P., Banerjee, S. S., Kenny, T. W., Santiago, J. G., and Goodson, K. E., 2001, “Modeling of Two-Phase Microchannel Heat Sinks for VLSI Chips,” 14th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2001), Interlaken, Switzerland, January 21–25, pp. 422–426. [CrossRef]
Steinke, M. E., and Kandlikar, S. G., 2004, “An Experimental Investigation of Flow Boiling Characteristics of Water in Parallel Microchannels,” ASME J. Heat Transfer, 126(4), pp. 518–526. [CrossRef]
Kandlikar, S. G., Kuan, W. K., Willistein, D. A., and Borrelli, J., 2006, “Stabilization of Flow Boiling in Microchannels Using Pressure Drop Elements and Fabricated Nucleation Sites,” ASME J. Heat Transfer, 128(4), pp. 389–396. [CrossRef]
Zhang, T., Peles, Y., Wen, J. T., Tong, T., Chang, J.-Y., Prasher, R., and Jensen, M. K., 2010, “Analysis and Active Control of Pressure-Drop Flow Instabilities in Boiling Microchannel Systems,” Int. J. Heat Mass Transfer, 53(11–12), pp. 2347–2360. [CrossRef]
Mukherjee, A., and Kandlikar, S. G., 2009, “The Effect of Inlet Constriction on Bubble Growth During Flow Boiling in Microchannels,” Int. J. Heat Mass Transfer, 52(21–22), pp. 5204–5212. [CrossRef]
Szczukiewicz, S., Borhani, N., and Thome, J. R., 2013, “Two-Phase Heat Transfer and High-Speed Visualization of Refrigerant Flows in 100 × 100 μm2 Silicon Microchannels,” Int. J. Refrig., 36(2), pp. 402–413. [CrossRef]
DARPA, 2013, “ICECool Applications,” Microsystems Technology Office, Defense Advanced Research Projects Agency, Arlington, VA, Solicitation Number DARPA-BAA-13-21, February 6.
Mukherjee, A., and Kandlikar, S. G., 2005, “Numerical Study of the Effect of Inlet Constriction on Bubble Growth During Flow Boiling in Microchannels,” ASME Paper No. ICMM2005-75143. [CrossRef]
Mukherjee, A., and Kandlikar, S. G., 2009, “The Effect of Inlet Constriction on Bubble Growth During Flow Boiling in Microchannels,” Int. J. Heat Mass Transfer, 52(21–22), pp. 5204–5212. [CrossRef]
Lu, C. T., and Pan, C., 2009, “A Highly Stable Microchannel Heat Sink for Convective Boiling,” J. Micromech. Microeng., 19(5), p. 055013. [CrossRef]
Miner, M. J., Phelan, P. E., Odom, B. A., Ortiz, C. A., Prasher, R. S., and Sherbeck, J. A., 2013, “Optimized Expanding Microchannel Geometry for Flow Boiling,” ASME J. Heat Transfer, 135(4), p. 042901. [CrossRef]
Kandlikar, S. G., Widger, T., Kalani, A., and Mejia, V., 2013, “Enhanced Flow Boiling Over Open Microchannels With Uniform and Tapered Gap Manifolds,” ASME J. Heat Transfer, 135(6), p. 061401. [CrossRef]
Yao, Z., Lu, Y.-W., and Kandlikar, S. G., 2012, “Fabrication of Nanowires on Orthogonal Surfaces of Microchannels and Their Effect on Pool Boiling,” J. Micromech. Microeng., 22(11), p. 115005. [CrossRef]
Yang, F., Dai, X., Peles, Y., Cheng, P., Khan, J., and Li, C., 2014, “Flow Boiling Phenomena in a Single Annular Flow Regime in Microchannels (I): Characterization of Flow Boiling Heat Transfer,” Int. J. Heat Mass Transfer, 68, pp. 703–715. [CrossRef]
Yang, F., Dai, X., Peles, Y., Cheng, P., Khan, J., and Li, C., 2014, “Flow Boiling Phenomena in a Single Annular Flow Regime in Microchannels (II): Reduced Pressure Drop and Enhanced Critical Heat Flux,” Int. J. Heat Mass Transfer, 68, pp. 716–724. [CrossRef]
Mizunuma, H., Yang, C.-L., and Lu, Y.-C., 2009, “Thermal Modeling for 3D-ICs With Integrated Microchannel Cooling,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2009), San Jose, CA, November 2–5, pp. 256–263.
Kearney, D., Hilt, T., and Pham, P., 2012, “A Liquid Cooling Solution for Temperature Redistribution in 3D IC Architectures,” Microelectron. J., 43(9), pp. 602–610. [CrossRef]
Zhang, J., Bloom field, M. O., Lu, J.-Q., Gutmann, R. J., and Cale, T. S., 2005, “Thermal Stresses in 3D IC Inter-Wafer Interconnects,” Microelectron. Eng., 82(3–4), pp. 534–547. [CrossRef]
Tu, K. N., 2011, “Reliability Challenges in 3D IC Packaging Technology,” Microelectronics Reliability, 51(3), pp. 517–523. [CrossRef]
Tilley, B. S., 2013, “On Microchannel Shapes in Liquid-Cooled Electronics Applications,” Int. J. Heat Mass Transfer, 62, pp. 163–173. [CrossRef]
Rubio-Jimenez, C. A., Kandlikar, S. G., and Hernandez-Guerrero, A., 2012, “Numerical Analysis of Novel Micro Pin Fin Heat Sink With Variable Fin Density,” IEEE Trans. Compon., Packag. Manuf., 2(5), pp. 825–833. [CrossRef]
Rubio-Jimenez, C. A., Kandlikar, S. G., and Hernandez-Guerrero, A., 2012, “Performance of Online and Offset Micro Pin-Fin Heat Sinks With Variable Fin Density,” IEEE Trans. Compon., Packag. Manuf., 3(1), pp. 86–93. [CrossRef]
Lorenzini-Gutierrez, D., and Kandlikar, S. G., “Numerical Simulation and Design of a Variable Density Flow Passage for Effective Cooling of a 3D IC Chip,” ASME J. Electron. Packag., 136(2), p. XXX. [CrossRef]
Ramm, P., Klumpp, A., and Weber, J., 2008, “3D Integration Technologies for MEMS/IC Systems,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2009), Capri, Italy, October 12–14, pp. 138–141. [CrossRef]
Ramm, P., and Klumpp, A., 2008, “Through-Silicon Via Technologies for Extreme Miniaturized 3D Integrated Wireless Sensor Systems (e-CUBES),” IEEE International Interconnect Technology Conference (IITC 2008), Burlingame, CA, June 1–4, pp. 7–9. [CrossRef]
Taklo, M. M. V., Lietaer, N., Tofteberg, H. R., Seppanen, T., Prainsack, J., Weber, J., and Ramm, P., 2009, “3D MEMS and IC Integration,” Materials Research Society Proceedings, 1112, pp. 211–220.
Gagnard, X., and Mourier, T., 2010, “Through Silicon Via: From the CMOS Imager Sensor Wafer Level Package to the 3D Integration,” Microelectron. Eng., 87(3), pp. 470–476. [CrossRef]
Xu, G., Huang, Q., Ning, W., Ruan, Z., and Luo, L., 2009, “A Novel MEMS Package With Three-Dimensional Stacked Modules,” International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP'09), Beijing, August 10–13, pp. 77–80. [CrossRef]
Floyd, B. A., Hung, C.-M., and O, K. K., 2002, “Intra-Chip Wireless Interconnect for Clock Distribution Implemented With Integrated Antennas, Receivers, and Transmitters,” IEEE J. Solid-State Circuits, 37(5), pp. 543–552. [CrossRef]
Ganguly, A., Chang, K., Deb, S., Pande, P. P., Belzer, B., and Teuscher, C., 2011, “Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems,” IEEE Trans. Comput., 60(10), pp. 1485–1502. [CrossRef]
Zhao, D., and Wang, Y., 2008, “SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip,” IEEE Trans. Comput., 57(9), pp. 1230–1245. [CrossRef]
More, A., and Taskin, B., 2011, “EM and Circuit Co-Simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs,” Proceedings of the IEEE 29th International Conference on Computer Design (ICCD), Amherst, MA, October 9–12, pp. 19–24. [CrossRef]
More, A., and Taskin, B., 2010, “Wireless Interconnects for Inter-Tier Communication on 3D ICs,” European Microwave Circuits Conference (EuMC), Paris, September 28–30, pp. 105–108.
More, A., and Taskin, B., 2010, “Simulation Based Study of On-Chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC,” IEEE International SOC Conference (SOCC), Las Vegas, NV, September 27–29, pp. 447–452. [CrossRef]
Lin, T-.Y., and Kandlikar, S. G., 2012, “An Experimental Investigation of Structured Roughness Effect on Heat Transfer During Single-Phase Liquid Flow at Microscale,” ASME J. Heat Transfer, 134(10), p. 101701. [CrossRef]
Li, Z., Hong, X., Zhou, Q., Bian, J., Yang, H., and Pitchumani, 2006, “Efficient Thermal-Oriented 3D Floor-Planning and Thermal Via Planning for Two-Stacked-Die Integration,” ACM Trans. Des. Autom. Electron. Syst.,” 11(2), pp. 325–345. [CrossRef]
Kudithipudi, D., Coskun, A., Reda, S., and Qiu, Q., 2012, “Temperature-Aware Computing: Achievements and Remaining Challenges,” IEEE 3rd International Green Computing Conference (IGCC), San Jose, CA, June 4–8, pp. 1–3. [CrossRef]
Mohanram, S., Brenner, D., and Kudithipudi, D., 2013, “Hierarchical Optimization of TSV Placement With Inter-Tier Liquid Cooling in 3D-IC MPSoCs,” 29th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), San Jose, CA, March 7–12, pp. 17–21. [CrossRef]
Kalani, A., and Kandlikar, S. G., 2013, “Experimental Investigation of Flow Boiling Performance of Open Microchannels With Uniform and Tapered Manifolds (OMM),” ASME Paper No. HT2013-17441. [CrossRef]
Garrou, P., 2011, “IBM to Use Water Cooling for Future 3D IC Processors,” Solid State Technol., 54(5), pp. 9.

Figures

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Fig. 1

A schematic representation of a 3D IC cooled with a coolant layer

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Fig. 2

A schematic of a three layer 3D IC structure with an external heat sink. Redrawn from Ref. [2].

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Fig. 3

A schematic representation of a microchannel cooled three layer 3D IC structure. Microchannels can be employed in both single phase and two-phase (evaporative) modes. Redrawn from Ref. [24].

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Fig. 4

Cross sectional view of the copper TSV passing through a silicon microchannel wall. Microchannel width 150 μm, height 200 μm, and TSV diameter 50 μm. Reprinted with permission from Sekar et al. [29].

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Fig. 5

Microchannels on a silicon chip glue bonded to a glass cover plate. Reprinted with permission from Dang et al. [30].

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Fig. 6

SEM micrographs showing polymeric micropipes adjacent to solder bumps. Reprinted with permission from Dang et al. [30].

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Fig. 7

Schematic of a proposed 3D IC stack cooled with microchannels with fluidic and TSV interconnects. Redrawn with permission from Dang et al. [30].

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Fig. 8

Schematic representation of through-plane microchannels between two coolant layers to cool hot spots. Redrawn with permission from Kearney et al. [58].

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Fig. 9

A conceptual 3D module with multiple microchannel cooling and active layers integrating wireless and TSV interconnects

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