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Technology Review

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

[+] Author and Article Information
Satish G. Kandlikar

Mechanical Engineering Department and
Microsystems Engineering Department,
Rochester Institute of Technology,
Rochester, NY 14623
e-mail: sgkeme@rit.edu

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 30, 2013; final manuscript received February 15, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie.

J. Electron. Packag 136(2), 024001 (Apr 29, 2014) (11 pages) Paper No: EP-13-1081; doi: 10.1115/1.4027175 History: Received July 30, 2013; Revised February 15, 2014

In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 μm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.

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Figures

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Fig. 1

A schematic representation of a 3D IC cooled with a coolant layer

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Fig. 2

A schematic of a three layer 3D IC structure with an external heat sink. Redrawn from Ref. [2].

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Fig. 3

A schematic representation of a microchannel cooled three layer 3D IC structure. Microchannels can be employed in both single phase and two-phase (evaporative) modes. Redrawn from Ref. [24].

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Fig. 4

Cross sectional view of the copper TSV passing through a silicon microchannel wall. Microchannel width 150 μm, height 200 μm, and TSV diameter 50 μm. Reprinted with permission from Sekar et al. [29].

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Fig. 5

Microchannels on a silicon chip glue bonded to a glass cover plate. Reprinted with permission from Dang et al. [30].

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Fig. 6

SEM micrographs showing polymeric micropipes adjacent to solder bumps. Reprinted with permission from Dang et al. [30].

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Fig. 7

Schematic of a proposed 3D IC stack cooled with microchannels with fluidic and TSV interconnects. Redrawn with permission from Dang et al. [30].

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Fig. 8

Schematic representation of through-plane microchannels between two coolant layers to cool hot spots. Redrawn with permission from Kearney et al. [58].

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Fig. 9

A conceptual 3D module with multiple microchannel cooling and active layers integrating wireless and TSV interconnects

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