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Technology Review

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

[+] Author and Article Information
Dapeng Liu

Mechanical Engineering,
State University of New York at Binghamton,
P.O. Box 6000,
Binghamton, NY 13902
e-mail: dliu5@binghamton.edu

Seungbae Park

Mechanical Engineering,
State University of New York at Binghamton,
P.O. Box 6000,
Binghamton, NY 13902
e-mail: sbpark@binghamton.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 7, 2013; final manuscript received January 27, 2014; published online February 18, 2014. Assoc. Editor: Shidong Li.

J. Electron. Packag 136(1), 014001 (Feb 18, 2014) (9 pages) Paper No: EP-13-1038; doi: 10.1115/1.4026615 History: Received May 07, 2013; Revised January 27, 2014

Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

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References

Figures

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Fig. 1

3D SiP with wire bonds and flip-chip bumps [1]

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Fig. 2

Cross section of a package with an interposer containing TSVs developed by Xilinx [8]

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Fig. 3

Cross section image showing interlocking Sn/Cu bumps (left) and a Cu planar bump with TSVs (right) [28]

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Fig. 4

Image of fabricated micro-inserts [29]

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Fig. 5

Solder transfer process in C4NP technology [21]

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Fig. 6

Cross section image of Cu-filled TSV with Cu microbump (a) and X-ray photo of TSVs after Sn plating (b) [43]

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Fig. 7

Schematic diagram of the SBM bumping process [45]

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Fig. 8

Cross section image showing TSVs and coined bumps [44]

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Fig. 9

A three-layer chip-stack fabricated with sequential reflow process by IBM [17]

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Fig. 10

A gap exposed by using a typical 50% corner fillet value in underfill dispensing [15]

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Fig. 11

SAM image of flip-chip samples after capillary (left) and vacuum (right) underfill dispensing [55]

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Fig. 12

Schematic diagram of the process flow of wafer-to-wafer hybrid bonding [66]

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Fig. 13

Cross section images of TSVs and microbumps [67]

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Fig. 14

SEM cross section image of the joint structure before (top) and after bonding (bottom) [69]

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Fig. 15

Comparison of the conventional joint structure and the WOW bumpless structure [71]

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Fig. 16

Process flow of the WOW bumpless interconnection technology [72]

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Fig. 17

A seven-layer wafer-stacking structure using the WOW process [73]

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Fig. 18

Schematic diagram of bonding an SOI wafer to the bottom wafer based on the IBM platform [76]

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Fig. 19

SEM image of a four-layer stack fabricated with SiO2 fusion bonding [77]

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Fig. 20

SEM cross section image showing a TSV connecting two bonded wafers [78]

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