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Research Papers

Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials

[+] Author and Article Information
S. A. Meguid

Fellow ASME
Mechanics and Aerospace Design Laboratory,
Mechanical and Industrial Engineering,
University of Toronto,
5 King's College Road,
Toronto, ON M5S 3G8, Canada
e-mail: meguid@mie.utoronto.ca

Chen Zhuo, Fan Yang

Mechanics and Aerospace Design Laboratory,
Mechanical and Industrial Engineering,
University of Toronto,
5 King's College Road,
Toronto, ON M5S 3G8, Canada

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received September 11, 2013; final manuscript received January 20, 2014; published online September 19, 2014. Assoc. Editor: Shidong Li.

J. Electron. Packag 136(4), 041010 (Sep 19, 2014) (9 pages) Paper No: EP-13-1102; doi: 10.1115/1.4026542 History: Received September 11, 2013; Revised January 20, 2014

Shock loads which are characterized by high intensity, short duration, and vibration at varied frequencies can lead to the failure of embedded electronics typically used to operate/control numerous devices. Failure of electronics renders these devices ineffective, since they cannot carry out their intended function. It is therefore the objective of this work to determine the behavior of a typical electronic board assembly subject to severe shock loads and the means to protect the electronics. Specifically, three aspects of the work were considered using 3D finite element (FE) simulations in supercomputer environment. The first was concerned with the dynamic behavior of selected electronic devices subject to shock loads. The second with the ability of different potting materials to attenuate the considered shock loads. The third was with the use of a new bilayer potting configurations to effectively attenuate the shock load and vibration of the electronic board. The shock loads were delivered to the Joint Electron Device Engineering Council (JEDEC) standard board using simulated drop impact test. The effectiveness of different protective potting designs to attenuate the effect of shock loads was determined by considering the two key factors of electronics reliability: the stress in the interconnection and deformation of the printed circuit board. Our results reveal the remarkable effectiveness of the bilayer potting approach over the commonly adopted single potting attenuation strategy.

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References

Figures

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Fig. 1

Configuration of JEDEC standard plate with 15 components

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Fig. 2

The FE impact model of PCB with IC components potted by a resin

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Fig. 3

(a) Unpotted case; (b) single layer potting configuration sectional view with the cutting plane parallel to X-Z plane; (c) bilayer potting configuration sectional view with the cutting plane parallel to X-Z plane

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Fig. 4

The interconnection stress history for unpotted case

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Fig. 5

The effect of various potting materials on the averaged stress in interconnection along impact direction

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Fig. 6

History curves of interconnection stresses for four representative components: (a) U1, (b) U3, (c) U6, and (d) U8 as indicated in Fig. 1 with various potting materials

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Fig. 7

The maximum PCB central deflection for different potting materials

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Fig. 8

History curves of PCB deflection at center for different potting materials

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Fig. 9

Effect of bilayer potting thickness ratio on (a) averaged interconnection stress along z-axis, and (b) maximum PCB central deflection

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Fig. 10

Effect of varied exterior potting modulus of bilayer potting on (a) averaged interconnection stress along z-axis and (b) maximum PCB central deflection

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Fig. 11

Effect of varied interior potting modulus of bilayer potting on (a) averaged interconnection stress along z-axis, and (b) maximum PCB central deflection

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Fig. 12

Illustration of the simple analytical model for three configurations: unpotted, single layer potting design, and bilayer potting design

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Fig. 13

(a) Contour plots of the normalized stress on the plane of the normalized moduli of the two potting layers, and (b) zoom-in plot. The unlabeled line indicates the same stress as the unpotted situation. The different dots mark the investigated potting cases in the simulations.

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