Shock loads which are characterized by high intensity, short duration, and vibration at varied frequencies can lead to the failure of embedded electronics typically used to operate/control numerous devices. Failure of electronics renders these devices ineffective, since they cannot carry out their intended function. It is therefore the objective of this work to determine the behavior of a typical electronic board assembly subject to severe shock loads and the means to protect the electronics. Specifically, three aspects of the work were considered using 3D finite element (FE) simulations in supercomputer environment. The first was concerned with the dynamic behavior of selected electronic devices subject to shock loads. The second with the ability of different potting materials to attenuate the considered shock loads. The third was with the use of a new bilayer potting configurations to effectively attenuate the shock load and vibration of the electronic board. The shock loads were delivered to the Joint Electron Device Engineering Council (JEDEC) standard board using simulated drop impact test. The effectiveness of different protective potting designs to attenuate the effect of shock loads was determined by considering the two key factors of electronics reliability: the stress in the interconnection and deformation of the printed circuit board. Our results reveal the remarkable effectiveness of the bilayer potting approach over the commonly adopted single potting attenuation strategy.