Research Papers

Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials

[+] Author and Article Information
S. A. Meguid

Fellow ASME
Mechanics and Aerospace Design Laboratory,
Mechanical and Industrial Engineering,
University of Toronto,
5 King's College Road,
Toronto, ON M5S 3G8, Canada
e-mail: meguid@mie.utoronto.ca

Chen Zhuo, Fan Yang

Mechanics and Aerospace Design Laboratory,
Mechanical and Industrial Engineering,
University of Toronto,
5 King's College Road,
Toronto, ON M5S 3G8, Canada

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received September 11, 2013; final manuscript received January 20, 2014; published online September 19, 2014. Assoc. Editor: Shidong Li.

J. Electron. Packag 136(4), 041010 (Sep 19, 2014) (9 pages) Paper No: EP-13-1102; doi: 10.1115/1.4026542 History: Received September 11, 2013; Revised January 20, 2014

Shock loads which are characterized by high intensity, short duration, and vibration at varied frequencies can lead to the failure of embedded electronics typically used to operate/control numerous devices. Failure of electronics renders these devices ineffective, since they cannot carry out their intended function. It is therefore the objective of this work to determine the behavior of a typical electronic board assembly subject to severe shock loads and the means to protect the electronics. Specifically, three aspects of the work were considered using 3D finite element (FE) simulations in supercomputer environment. The first was concerned with the dynamic behavior of selected electronic devices subject to shock loads. The second with the ability of different potting materials to attenuate the considered shock loads. The third was with the use of a new bilayer potting configurations to effectively attenuate the shock load and vibration of the electronic board. The shock loads were delivered to the Joint Electron Device Engineering Council (JEDEC) standard board using simulated drop impact test. The effectiveness of different protective potting designs to attenuate the effect of shock loads was determined by considering the two key factors of electronics reliability: the stress in the interconnection and deformation of the printed circuit board. Our results reveal the remarkable effectiveness of the bilayer potting approach over the commonly adopted single potting attenuation strategy.

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Viswanadham, P., and Singh, P., 1998, Failure Modes and Mechanisms in Electronic Packaging, Thomson Science, New York.
Zhu, L., and Marcinkiewicz, W., 2005, “Drop Impact Reliability Analysis of CSP Packages at Board and Product System Levels Through Modeling Approaches,” IEEE Trans. Compon. Packag. Technol., 28(3), pp. 449–456. [CrossRef]
Wong, E. H., Seah, S. K. W., and Shim, V. P. W., 2008, “A Review of Board Level Solder Joints for Mobile Applications,” Microelectron. Reliab., 48(11–12), pp. 1747–1758. [CrossRef]
Wong, E. H., Seah, S. K. W., van Driel, W. D., Caers, J. F. J. M., Owens, N., and Lai, Y. S., 2009, “Advances in the Drop-Impact Reliability of Solder Joints for Mobile Applications,” Microelectron. Reliab., 49(2), pp. 139–149. [CrossRef]
Nunziato, J. W., and Schuler, K. W., 1973, “Shock Pulse Attenuation in a Nonlinear Viscoelastic Solid,” J. Mech. Phys. Solids, 21(6), pp. 447–457. [CrossRef]
Chen, Y., Zhang, Z., Wang, Y., Hua, H., and Gou, H., 2009, “Attenuating Performance of a Polymer Layer Coated Onto Floating Structures Subjected to Water Blasts,” Eur. J. Mech. A, 28(3), pp. 591–598. [CrossRef]
Ardebili, H., and Pecht, M. G., 2009, Encapsulation Technologies for Electronic Applications, William Andrew, Oxford, UK.
Harrison, J. C., 1977, “Control of the Encapsulation Material as an Aid to Long Term Reliability in Plastic Encapsulated Semiconductor Components,” Microelectron. Reliab., 16(3), pp. 233–244. [CrossRef]
Kinjo, N., Ogata, M., Nishi, K., and Kaneda, A., 1989, “Epoxy Molding Compounds as Encapsulation Materials for Microelectronic Devices,” Adv. Polym. Sci., 88, pp. 1−48. [CrossRef]
Ketcham, C., 1998, “Printed Circuit Packaging for High Vibration and Temperature Environments,” U.S. Patent No. 4768286.
Benson, R. C., Farrar, D., and Miragliotta, J. A., 2008, “Polymer Adhesives and Encapsulants for Microelectronic Applications,” Johns Hopkins APL Tech. Dig., 28(1), pp. 58−71.
Goth, C., Franke, J., Reinhardt, A., and Widemann, P., 2012, “Reliability of Molded Interconnect Devices (MID) Protected by Encapsulation Methods Overmolding, Potting and Coating,” 7th International Conference on Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), Taipei, Taiwan, October 24–26, pp. 137−140. [CrossRef]
Birkelund, K., Nørgaard, L., and Thomsen, E. V., 2011, “Enhanced Polymeric Encapsulation for MEMS Based Multi Sensors for Fisheries Research,” Sens. Actuators, A, 170(1–2), pp. 196–201. [CrossRef]
Neidigk, M., 2012, “Numerical Analysis of Surface Mount Electronics With Viscoelastic Epoxy Underfills and Potting,” Ph.D. thesis, University of New Mexico, Albuquerque, NM.
Jenq, S. T., Sheua, H. S., Yeh, C. L., Lai, Y. S., and Wu, J. D., 2007, “High-G Drop Impact Response and Failure Analysis of a Chip Packaged Printed Circuit Board,” Int. J. Impact Eng., 34(10), pp. 1655–1667. [CrossRef]
Steinberg, D. S., 2000, Vibration Analysis for Electronic Equipment, 3rd ed., John Wiley & Sons, New York.
Jiang, Y., Du, M., Huang, W., Xu, W., and Luo, L., 2003, “Simulation on the Encapsulation Effect of the High-G Shock MEMS Accelerometer,” 5th International Conference on Electronic Packaging Technology (ICEPT 2003), Shanghai, China, October 28–30, pp. 52–55. [CrossRef]
Jiang, Y., Du, M., Luo, L., and Li, X. X., 2004, “Simulation of the Potting Effect on the High-G MEMS Accelerometer,” J. Electron. Mater., 33(8), pp. 893–899. [CrossRef]
Chao, N. H., Cordes, J. A., Carlucci, D., de Angelis, M. E., and Lee, J., 2011, “The Use of Potting Materials for Electronic-Packaging Survivability in Smart Munitions,” ASME J. Electron. Packag., 133(4), p. 041003. [CrossRef]
Haynes, A., and Cordes, J. A., 2011, “Characterization of a Potting Material for Gun Launch,” 26th International Symposium on Ballistics, Miami, FL, September 12–16, E.Baker and D.Templeton, eds., DEStech Publications Inc., Lancaster, PA, pp. 1038–1041.
Reinhardt, L. E., Cordes, J. A., Haynes, A. S., and Metz, J. D., 2013, “Assessment of Need for Solder in Modeling Potted Electronics During Gun-Shot,” ASME J. Appl. Mech., 80(3), p. 031502. [CrossRef]
Haynes, A. S., Cordes, J. A., and Krug, J., 2013, “Thermomechanical Impact of Polyurethane Potting on Gun Launched Electronics,” J. Eng., 2013, p. 148362. [CrossRef]
Clelland, I. W., PriceR. A., and Jelonek, P. R., 2012, “Double Layer Capacitor Using Polymer Electrolyte in Multilayer Construction,” U.S. Patent No. US8098482 B2.
Chattopadhyay, S., and Meredith, J. C., 2004, “Instability and Dewetting of Conducting-Insulating Polymer Thin-Film Bilayers,” Macromol. Rapid Commun., 25(1), pp. 275–279. [CrossRef]
Carlson, J., 2003, “Board Level Drop Test Method of Component for Handheld Electronic Products,” JEDEC Solid State Technology Association, Arlington, VA, Paper No. JESD22-B111.
“SHARCNET: Welcome,” 2009, SHARCNET, London, ON, Canada, www.sharcnet.ca. Last accessed on September 8th 2013.
Tsai, T. Y., Lai, Y. S., Yeh, C. L., and Chen, R. S., 2008, “Structural Design Optimization for Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages,” Microelectron. Reliab., 48(5), pp. 757–762. [CrossRef]
Yang, F., and Meguid, S. A., 2013, “Efficient Multi-Level Modelling Technique for Determining Effective Board Drop Reliability of PCB Assembly,” Microelectron. Reliab., 53(7), pp. 975–984. [CrossRef]
Zhang, S., Panat, R., and Hsia, K. J., 2003, “Influence of Surface Morphology on the Adhesive Strength of Aluminum/Epoxy Interfaces,” J. Adhes. Sci. Technol., 17(12), pp. 1685–1711. [CrossRef]
Dassault Systèmes, 2011, ABAQUS Documentation Version 6.11.
Chong, D. Y. R., Che, F. X., Pang, J. H. L., Ng, K., Tan, J. Y. N., and Low, P. T. H., 2006, “Drop Impact Reliability Testing for Lead-Free and Lead-Based Soldered IC Packages,” Microelectron. Reliab., 46(7), pp. 1160–1171. [CrossRef]
Wong, E. H., Lim, K. M., Lee, N., Seah, S., Hoe, C., and Wang, J., 2002, “Drop Impact Test—Mechanics & Physics of Failure,” 4th Electronics Packaging Technology Conference (EPTC), Singapore, December 10–12, pp. 327–333. [CrossRef]
Yu, D., Kwak, J., Park, S., Chung, S., and Yoon, J. Y., 2012, “Effect of Shield-Can on Dynamic Response of Board-Level Assembly”, ASME J. Electron. Packag., 134(3), p. 031010. [CrossRef]
Kwak, J., Yu, D., Park, S., Chung, S., Yoon, J. Y., and Jang, K. W., 2010, “Effect of Shield-Can for Drop/Shock Behavior of Board Level Assembly,” 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Las Vegas, NV, June 2–5. [CrossRef]


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Fig. 1

Configuration of JEDEC standard plate with 15 components

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Fig. 2

The FE impact model of PCB with IC components potted by a resin

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Fig. 3

(a) Unpotted case; (b) single layer potting configuration sectional view with the cutting plane parallel to X-Z plane; (c) bilayer potting configuration sectional view with the cutting plane parallel to X-Z plane

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Fig. 4

The interconnection stress history for unpotted case

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Fig. 5

The effect of various potting materials on the averaged stress in interconnection along impact direction

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Fig. 6

History curves of interconnection stresses for four representative components: (a) U1, (b) U3, (c) U6, and (d) U8 as indicated in Fig. 1 with various potting materials

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Fig. 7

The maximum PCB central deflection for different potting materials

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Fig. 8

History curves of PCB deflection at center for different potting materials

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Fig. 9

Effect of bilayer potting thickness ratio on (a) averaged interconnection stress along z-axis, and (b) maximum PCB central deflection

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Fig. 10

Effect of varied exterior potting modulus of bilayer potting on (a) averaged interconnection stress along z-axis and (b) maximum PCB central deflection

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Fig. 11

Effect of varied interior potting modulus of bilayer potting on (a) averaged interconnection stress along z-axis, and (b) maximum PCB central deflection

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Fig. 12

Illustration of the simple analytical model for three configurations: unpotted, single layer potting design, and bilayer potting design

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Fig. 13

(a) Contour plots of the normalized stress on the plane of the normalized moduli of the two potting layers, and (b) zoom-in plot. The unlabeled line indicates the same stress as the unpotted situation. The different dots mark the investigated potting cases in the simulations.




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