Technical Brief

Thermal Analysis of Air-Cooled Electronic Units With Integrated Offset Strip-Fin Heat Sink

[+] Author and Article Information
Bengt Sundén

Division of Heat Transfer,
Department of Energy Sciences,
Lund University,
P.O. Box 118,
Lund SE-22100, Sweden
e-mail: bengt.sunden@energy.lth.se

Gongnan Xie

Engineering Simulation and Aerospace
Computing (ESAC),
The Key Laboratory of Contemporary Design
and Integrated Manufacturing Technology,
Northwestern Polytechnical University,
P.O. Box 552,
Xi'an, Shaanxi 710072, China
e-mail: xgn@nwpu.edu.cn

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received June 29, 2013; final manuscript received January 12, 2014; published online April 29, 2014. Assoc. Editor: Gary Miller.

J. Electron. Packag 136(2), 024501 (Apr 29, 2014) (5 pages) Paper No: EP-13-1058; doi: 10.1115/1.4026538 History: Received June 29, 2013; Revised January 12, 2014

This short communication addresses a numerical investigation of the thermal behavior of an electronic unit. The unit consists of several parallel planes and on the top and bottom planes heat is generated by a number of electronic chips. The heat is transported by conduction through plastic and copper-invar layers. Finally, the heat is rejected by a forced air stream in the center of the unit. The channel system for the cooling air is designed as an offset strip fin surface. A three-dimensional numerical method based on a thermal resistance or conductance network has been developed. The grid points on the cooling air side are staggered compared to the grid points in the solid materials. Details of the numerical method as well as some temperature distributions on the chip planes are provided.

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Fig. 1

Principal sketch of an air-cooled chassi

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Fig. 2

(a) Sketch of the considered electronic unit and the cooling system and (b) thermal resistance or conductance network

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Fig. 3

Offset strip fin insert

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Fig. 4

Coordinate system shown on a chip plane

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Fig. 6

Staggered grid arrangement

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Fig. 9

Temperature distribution, upper plane

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Fig. 10

Temperature distribution, lower plane




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