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Research Papers

Heterogeneous Void Nucleation Study in Flip Chip Assembly Process Using No-Flow Underfill

[+] Author and Article Information
Sangil Lee

The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332-0405

Daniel F. Baldwin

The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332-0405

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 6, 2012; final manuscript received October 19, 2013; published online December 31, 2013. Assoc. Editor: Koneru Ramakrishna.

J. Electron. Packag 136(1), 011005 (Dec 31, 2013) (6 pages) Paper No: EP-12-1068; doi: 10.1115/1.4026164 History: Received July 06, 2012; Revised October 19, 2013

No-flow underfill process has exhibited a narrow feasible process window due to electrical assembly yield loss or underfill voiding. In general, the assembly yield can be improved using reflow process designed at high temperature, while the high temperature condition potentially causes serious underfill voiding. Typically, the underfill voiding can result in critical defects, such as solders fatigue cracking or solders bridge, causing early failures in thermal reliability. Therefore, this study reviews a classical bubble nucleation theory to model voids nucleation during reflow process. The established model designed a reflow process possibly preventing underfill voiding. The reflow process was validated using systematic experiments designed on the theoretical study with a commercial high I/O counts (5000>), fine-pitch (<150 μm) flip chip. The theoretical model exhibits good agreement with experimental results. Thus, this paper presents systematic studies through the use of structured experimentation designed to achieve a high, stable yield, and void-free assembly process on the classical bubble nucleation theory.

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Figures

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Fig. 5

(a) Top-view of schematic of a typical test vehicle configuration used for heterogeneous nucleation and (b) cross-sectional view of the schematic of a test vehicle

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Fig. 4

Variation of ΔG with r for a heterogeneous nucleation

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Fig. 2

Micrographs of FCIP built using no-flow underfill material under the reflow conditions of ramp rate: 2.1 °C/s, reflow time: 70 s, peak temperature 225 °C

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Fig. 1

Flip chip assembly process using no-flow underfills [17]

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Fig. 3

The schematic of heterogeneous bubble nucleation on smooth surface

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Fig. 6

Typical no-flow underfill reflow profile

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Fig. 7

Micrograph of a typical visually magnified test vehicle with 15 nucleated voids after heating at 230 °C

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Fig. 9

Micrographs of reflow process characterization at: (a) 180 °C, (b) 190 °C, (c) 200 °C, and (d) 220 °C

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Fig. 10

Micrographs of reflow process validation at ramp rate: 1.3 °C/s; soak time (120–130 °C): 120 s; time above liquidus: 90 s; and peak temperature: 190 °C. (a) C-SAM and (b) planar-sectional view

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Fig. 8

Void nucleation rate versus 1/T (temperature)

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