0
Research Papers

Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias

[+] Author and Article Information
Anjali Chauhan

e-mail: achauha1@binghamton.edu

Bahgat Sammakia

e-mail: bahgat@binghamton.edu

Furat F. Afram

e-mail: fafram1@binghamton.edu

Kanad Ghose

e-mail: ghose@cs.binghamton.edu

Gamal Refai-Ahmed

Professor
e-mail: gra1963@yahoo.com

Small Scale Systems Integration and Packaging Center,
SUNY,
Binghamton, NY 13902

Dereje Agonafer

Department of Mechanical and
Aerospace Engineering,
University of Texas at Arlington,
Arlington, TX 76019
e-mail: agonafer@uta.edu

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received November 30, 2012; final manuscript received August 8, 2013; published online November 5, 2013. Assoc. Editor: Mehmet Arik.

J. Electron. Packag 135(4), 041006 (Nov 05, 2013) (14 pages) Paper No: EP-12-1106; doi: 10.1115/1.4025531 History: Received November 30, 2012; Revised August 08, 2013

The electronics industry is heading toward the three-dimensional (3D) microprocessor to cope with higher computing workloads. The 3D stacking of the processor and the memory components reduces the communication delay in multicore system-on-a-chip (SoCs), owing to reduced system size and shorter interconnects. The shorter interconnects in a multicore system lowers the memory access latencies and contributes to improvements in memory access bandwidth. The shorter interconnects in stacked architectures also enables small drivers for interconnections which further reduce interconnection-level-energy dissipations. On the down side, the 3D-stacked architectures have high thermal resistance, which in conjunction with poor thermal management techniques, poses a thermal threat to the reliability of the device. This paper establishes the significance of the microprocessor floor planning and single-phase microchannel cooling for solving the thermal issues arising in the 3D-stacked-quad-core processor. The 3D-stacked-quad-core processor considered in this study comprises of symmetric nonuniformly powered quad-core processor, liquid-cooled microchannel heat sink, dynamic random access memory (DRAM), thermal interface material (TIM), and heat spreader. The electrical through-silicon-vias (TSVs) between the processor and DRAM serve as interconnects, while the thermal TSVs reduce the internal thermal resistance. The effective cooling of the 3D-stacked-quad-core processor depends on the TSVs, quad-core layout and the optimized design of the microchannel heat sink for the desired coolant. The microchannel cooling of the 3D-stacked processor is done both by planar flow and impingement flow. The thermal efficiency of the cooling techniques is evaluated on the basis of hot spot temperature, hot spot spread, and number of hot spots.

Copyright © 2013 by ASME
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Fig. 3

Nuavg plotted axially for constant q″ on channel walls, fluid ΔPt = 3.45 kPa

Grahic Jump Location
Fig. 2

Numerical model of the quad-core processor with microchannel heat sink on its top (not drawn to scale)

Grahic Jump Location
Fig. 1

3D model for stacked quad-core processor and DRAM. All dimensions are in mm (not drawn to scale).

Grahic Jump Location
Fig. 4

Microprocessor floor plan: (a) base floorplan and (b) optimized floorplan

Grahic Jump Location
Fig. 5

Symmetric layout of the quad-core processor: (a) layout-1 and (b) layout-2

Grahic Jump Location
Fig. 6

BQCL-1 (a) flux profile (W/m2) of the chip, y = 0 mm (b) Tsurf (°C) contours, y = 0.2 mm for horizontal flow (c) Tsurf (°C) contours, y = 0.2 mm for vertical flow. Fluid ΔPt = 3.45 kPa.

Grahic Jump Location
Fig. 7

BQCL-2 (a) flux profile (W/m2) of the chip, y = 0 mm (b) Tsurf (°C) contours, y = 0.2 mm for horizontal flow (c) Tsurf (°C) contours, y = 0.2 mm for vertical flow. Fluid ΔPt = 3.45 kPa.

Grahic Jump Location
Fig. 8

OQCL-1 (a) flux profile (W/m2) on the chip, y = 0 mm; (b) Tsurf (°C) contours, y = 0.2 mm for horizontal flow. Fluid ΔPt = 3.45 kPa.

Grahic Jump Location
Fig. 9

OQCL-2 (a) flux profile (W/m2) on the chip, y = 0 mm; (b) Tsurf (°C) contours, y = 0.2 mm for horizontal flow. Fluid ΔPt = 3.45 kPa.

Grahic Jump Location
Fig. 10

Variation of (a) Tsurf, hot spot and (b) Tsurf, area-avg on the chip surface with the Wch of the microchannel heat sink. Fluid ΔPt = 3.45 kPa.

Grahic Jump Location
Fig. 13

Impingement cooling of the quad-core processor. Tsurf (°C) contours on the chip surface at y = 0.2 mm. (a) BQCL-1 and (b) OQCL-1. Fluid ΔPt = 3.45 kPa.

Grahic Jump Location
Fig. 14

Impingement flow, Thotspot as a function of ΔPt

Grahic Jump Location
Fig. 15

2D view of the 3D-stacked quad-core processor. All dimensions are in mm (not drawn to scale).

Grahic Jump Location
Fig. 11

Planar flow, Thotspot as a function of ΔPt

Grahic Jump Location
Fig. 12

Numerical model of the quad-core processor for impingement flow (a) 2D view and (b) 3D view. All dimensions are in mm (not drawn to scale).

Grahic Jump Location
Fig. 18

2D view of the 3D-stacked quad-core processor for impingement cooling. All dimensions are in mm (not drawn to scale).

Grahic Jump Location
Fig. 19

Impingement cooling of the 3D-stacked quad-core processor with BQCL-1 (a) Tsurf (°C) contours on chip surface, y = 0.2 mm; (b) Tsurf (°C) contours on DRAM surface, y = 0.4 mm. Fluid ΔPt = 1.725 kPa.

Grahic Jump Location
Fig. 20

Impingement cooling of the 3D-stacked quad-core processor with OQCL-1 (a) Tsurf (°C) contours on chip surface, y = 0.2 mm; (b) Tsurf (°C) contours on DRAM surface, y = 0.4 mm. Fluid ΔPt = 1.725 kPa.

Grahic Jump Location
Fig. 16

Planar cooling of 3D-stacked processor with BQCL-1 (a) Tsurf (°C) contours on chip surface, y = 0.2 mm; (b) Tsurf (°C) contours on DRAM surface, y = 0.4 mm. Fluid ΔPt = 1.725 kPa.

Grahic Jump Location
Fig. 17

Planar cooling of 3D-stacked processor with OQCL-1 (a) Tsurf (°C) contours on chip surface, y = 0.2 mm; (b) Tsurf (°C) contours on DRAM surface, y = 0.4 mm. Fluid ΔPt = 1.725 kPa.

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In