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Research Papers

3D Compact Model of Packaged Thermoelectric Coolers

[+] Author and Article Information
Owen Sullivan, Satish Kumar

G. W. Woodruff School of Mechanical
Engineering, Georgia Institute of Technology,
Atlanta, GA 30332

Saibal Mukhopadhyay

Department of Electrical and
Computer Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the Journal of Electronic Packaging. Manuscript received January 15, 2013; final manuscript received April 24, 2013; published online June 24, 2013. Assoc. Editor: Amy Fleischer.

J. Electron. Packag 135(3), 031006 (Jun 24, 2013) (7 pages) Paper No: EP-13-1006; doi: 10.1115/1.4024653 History: Received January 15, 2013; Revised April 24, 2013

Hotspots on a microelectronic package can severely hurt the performance and long-term reliability of the chip. Thermoelectric coolers (TECs) can provide site-specific and on-demand cooling of hot spots in microprocessors. We develop a 3D compact model for fast and accurate modeling of a TEC device integrated inside an electronic package. A 1D compact model of a TEC is first built in SPICE and validated for steady-state and transient behavior against a finite-volume model. The 1D compact model of the TEC is then incorporated into a 3D compact model of a prototype electronic package. The results from the compact model for the packaged TEC are in good agreement with a finite-volume based model, which confirms the compact model's ability to accurately model the TEC's interaction with the package. Analysis of packaged TECs using this 3D compact model shows that (i) moving TECs closer to the chip results in faster response time and an increase in maximum cooling, (ii) high thermal contact resistance within the thermoelectric cooler significantly degrades performance of the device, and (iii) higher convective heat transfer coefficients (HTC) at the heat spreader surface increase steady-state cooling but decrease maximum transient cooling.

Copyright © 2013 by ASME
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References

Figures

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Fig. 1

Schematic of the electronic package with integrated TEC

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Fig. 2

One-dimensional steady-state compact model of the thermoelectric cooled integrated inside package; top node of TEC connects to the ambient through a heat spreader

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Fig. 3

Steady-state validation of the 1D compact model (dashed lines) against the 1D finite-volume model (solid lines) at varying current. Temperatures at bottom of chip (source of heat flux), bottom of TEC superlattice (cold side), and top of TEC superlattice (hot side) are compared.

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Fig. 4

Relative steady-state error between the finite-volume model and compact model for various currents

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Fig. 5

Validation of the transient temperature behavior obtained from 1D compact model (dashed lines) against the 1D finite-volume model (solid lines) at varying currents; temperature is measured at the bottom of chip

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Fig. 6

Relative error for time varying peak temperature at the bottom surface of the chip computed from the finite-volume method and compact models at various currents

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Fig. 7

Sample “mesh” and the accompanying resistor–capacitor network model for a single cell of chip or electronic package (∼chip, TIM, or heat spreader); abbreviations stand for north (N), south (S), east (E), west (W), top (T), bottom (B), and center (C)

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Fig. 8

Multiplier for additional resistance of larger heat spreader versus spreader length (mm)

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Fig. 9

Steady-state validation of the compact model of TEC integrated inside an electronic package (using equivalent spreader resistance (dashed line) against finite-volume model (solid line) at various currents. The comparison is done for temperature at the center of the chip, directly below the location of TEC.

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Fig. 10

Transient validation of the compact model of TEC integrated inside an electronic package (using equivalent spreader resistance; dashed lines) against the finite-volume model (solid lines) for currents varying from 0 A to 12 A. The comparison is done for temperature at the center of the chip, directly below the location of TEC.

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Fig. 11

Effect of thickness of TIM material between chip and bottom of TEC device on the transient behavior of the TEC device with a current of 8 A; five thicknesses are tested: 24 μm, 12 μm, 6 μm, 3 μm, and 0 μm

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Fig. 12

Effect of thermal contact resistance within TEC on transient performance of the TEC device for various thermal contact resistances between copper and superlattice layers and constant TEC current of 8 A; thermal contact resistances are in the range of 1 × 10−6–7.5 × 10−6 m2 K/W

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Fig. 13

Maximum steady-state cooling and associated currents for various HTC at top surface of heat spreader; HTC is varied in the range of 1000 W/m2 K to 20,000 W/m2 K

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Fig. 14

Maximum transient cooling (ΔT) and steady-state temperature (SST) with zero TEC current for various heat transfer coefficients at top surface of heat spreader, varying from 1000 W/m2 K to 20,000 W/m2 K; maximum cooling occurred at 7.5 A and 0.045 s for all cases

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Fig. 15

Contour plots of ΔTp at the bottom surface of chip, using the 3D compact model, for convective heat transfer coefficients 1000 W/m2 K and 10,000 W/m2 K at three different time steps: 0 ms, 25 ms, and 45 ms. Here, for each convection coefficient, ΔTp is estimated as temperature difference with respect to the peak temperature on chip at t = 0 ms.

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