Research Papers

Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

[+] Author and Article Information
Suresh K. Sitaraman

e-mail: suresh.sitaraman@me.gatech.edu
The George W. Woodruff School of Mechanical Engineering,
Georgia Institute of Technology,
Atlanta, GA 30332-0405

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received November 19, 2012; final manuscript received March 23, 2013; published online June 4, 2013. Assoc. Editor: Yi-Shao Lai.

J. Electron. Packag 135(3), 031004 (Jun 04, 2013) (7 pages) Paper No: EP-12-1102; doi: 10.1115/1.4024112 History: Received November 19, 2012; Revised March 23, 2013

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

Copyright © 2013 by ASME
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Fig. 3

SEM images of intermediate fabrication steps: (a) first layer photoresist showing mold cavity for post, (b) partially plated post with second seed layer, and (c) released free-standing interconnects

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Fig. 4

SEM images of 100 -μm pitch dual-path compliant interconnects

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Fig. 5

Schematic illustrating the experimental compliance measurement using a fabricated dual-path interconnect

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Fig. 6

Experimental force–displacement curve of fabricated interconnect

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Fig. 2

Fabrication steps for dual-path interconnect

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Fig. 1

Interconnect dimensions and members (use μm)

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Fig. 7

Fabricated beam dimensions

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Fig. 8

Simulated force–displacement curve of as fabricated interconnect

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Fig. 9

CAD model of interconnect for compliance measurement

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Fig. 10

Generalized plane displacement model

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Fig. 11

Shows the equivalent strain distribution at 0 °C (i.e., highest strain levels)

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Fig. 12

Die backside principal stresses in a 20 mm × 20 mm assembly at 0  °C



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