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Research Papers

Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies

[+] Author and Article Information
Wataru Nakayama

Fellow ASME
ThermTech International,
920-7 Higashi Koiso,
Oh-Iso Machi,
Kanagawa 255-0004, Japan
e-mail: watnakayama@aol.com

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 26, 2012; final manuscript received November 7, 2012; published online March 28, 2013. Assoc. Editor: Stephen McKeown.

J. Electron. Packag 135(2), 021003 (Mar 28, 2013) (16 pages) Paper No: EP-12-1032; doi: 10.1115/1.4023292 History: Received February 26, 2012; Revised November 07, 2012

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

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Figures

Grahic Jump Location
Fig. 1

Heat flux and area data from Refs. [6-8]. The vertical axis is the ratio of heat flux on individual functional unit to the average heat flux on the whole units or the die. The horizontal axis is the ratio of unit area to whole area. Also plotted are some of the data from the power scenarios used in the case studies of Sec. 4; the triangles on a curve are the data of the white-space-dominant scenario (rp,0 = 0.3, rp,k = 0 for k ≥ 1), and the squares on another curve are those of the self-similar scenario (rp,k = 0.3 for all k).

Grahic Jump Location
Fig. 2

Sketches of representative thermal environment for the die; (a) high-performance air-cooling, (b) conventional air-cooling, (c) high-performance liquid-cooling, (d) oil-cooling in IR measurement setup, and (e) a die in passively cooled casing

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Fig. 3

Data of thermal resistance of air-cooled finned heat sinks collected from the literature and various commercial sources. The curve represents a correlation (5) which is used to form the parameters set for the case studies of Sec. 4. The line 0.1 K/W represents the target of research for finned heat sinks [31].

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Fig. 4

Hierarchical layout of active and background cells on the die. The dimensions are used in the case studies reported in Sec. 4; the die footprint is 20 mm × 20 mm, the target spot of temperature calculation is at 13.3 mm from the corner of the die in both the horizontal and vertical directions.

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Fig. 5

A three-layer model on which the heat conduction analysis is performed. On the die body (layer 1), the buried oxide (layer 2), and the wiring layer (layer 3) are stacked. The heat source plane is between the oxide and the wiring layers. The plan view (in the upper part of the figure) shows the footprint of the pilot heat source and a patch cell. The solution of this problem is used in several ways to construct the system of temperature calculations.

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Fig. 6

Temperatures of the focal cell (θHS,k) and the background cell at the corner edge of the die (θmin), and their difference denoted as the temperature contrast (ΔθHS,k). The case is {“AC,” “Ref”} with the white-space-dominant scenario (rp,0 = 0.3, rp,k = 0 for k ≥ 1). The granularity level indexes are also shown. The horizontal axis is the normalized cell length.

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Fig. 7

Heat flux on focal cell, and temperature contrast over the die in the case “AC”, plotted against the normalized cell length. (a) Heat fluxes for the white-space-dominant scenario (solid curve) and the self-similar scenario (broken curve). (b) Temperature contrasts for the two scenarios. Only in the white-space-dominant scenario the curves diverge in the range of fine granularities depending on the layer organization (Ref, Bulk, and No Wire).

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Fig. 8

Heat flux on focal cell, and temperature contrast over the die for all cases of cooling condition under the white-space-dominant scenario. (a) Heat flux versus the normalized cell length. (b) Temperature contrast versus the normalized cell length.

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Fig. 9

The ratio of heat flow from the focal cell to layer 3 (QU,k) to level-k excess heat (Qe,k) under the white-space-dominant scenario. The horizontal axis is the normalized cell length. (a) Case AC (high-performance air-cooling). (b) Case PC (a die in passively cooled casing).

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