Research Papers

Study on Heat Conduction in a Simulated Multicore Processor Chip—Part I: Analytical Modeling

[+] Author and Article Information
Wataru Nakayama

Fellow ASME
ThermTech International,
920-7 Higashi Koiso,
Oh-Iso Machi,
Kanagawa 255-0004, Japan
e-mail: watnakayama@aol.com

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 26, 2012; final manuscript received November 7, 2012; published online March 28, 2013. Assoc. Editor: Stephen McKeown.

J. Electron. Packag 135(2), 021002 (Mar 28, 2013) (16 pages) Paper No: EP-12-1031; doi: 10.1115/1.4023291 History: Received February 26, 2012; Revised November 07, 2012

A system of temperature calculations is developed to study the conditions leading to hot spot occurrence on multicore processor chips. The analysis is performed on a physical model which incorporates certain salient features of multicore processor. The model has active and background cells laid out in a checkered pattern, and the pattern repeats itself in fine grain active cells. The die has a buried dioxide and a wiring layer stacked on the die body, and heat sources are placed at the wiring layer/buried oxide interface. With this model we explore the effects of various parameters on the target spot temperature. The parameters are the die dimensions, the materials' thermal conductivities, the effective heat transfer coefficients on the die surfaces, the power map, and the spatial resolution with which we view the power and temperature distributions on the die. Closed-form analytical solutions are derived and used to examine the roles of these parameters in creating hot spots. The present paper reports the details of mathematical formulations and steps of temperature calculation. The results for a particular example case are included to illustrate what can be learned from the calculations.

Copyright © 2013 by ASME
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Fig. 1

“Floor plan” of the simulated multicore processor

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Fig. 2

Global flow of analysis

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Fig. 3

Distribution of power “bricks” in the transition step from level-k to level-(k + 1) analysis

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Fig. 4

Zooming step based on the temperature distribution created by placing the pilot heat source on the focal cell location and calculating area-averaged temperatures of cells in row

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Fig. 5

Steps to calculate contributions of heat from active cells to the temperature rise of the focal cell (F) in the common mother cell. The pilot heat source is placed at locations of active cells and the area-averaged temperature at F is calculated. Only two instances with active cells A and B are shown.

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Fig. 6

Flux tube model. The analytical solution on this model is used in several ways in the entire calculation flow.

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Fig. 7

Integer coordinate systems (〈ik〉, 〈jk〉) attached to level-k zoomed zone, and (is,k+1, js,k+1) attached to level-(k + 1) focal cell. (xs,k, ys,k) is the location of the center of the focal cell measured from the lower left corner of level-k zoomed zone. (〈IEk〉, 〈JNk〉) and (〈IWk〉, 〈JSk〉) define the boundary of level-(k + 1) zoomed zone.

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Fig. 9

Thermal resistance component (ψk + Δψk) versus the normalized cell length (lk/ld). Labels “Ref,” “Bulk,” “No wire” signify the on-chip layer organization. Locations of granularity levels are also included.

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Fig. 8

Steps to calculate the target spot temperature θHS,K. Equations to be used are identified by their numbers in the text.




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