Research Papers

Monitoring Fatigue Cracking in Interconnects in a Ball Grid Array by Measuring Electrical Resistance

[+] Author and Article Information
B. Fiedler, M. Fine

Northwestern University, Materials Science and Engineering Department, 2220 Campus Drive, Evanston, IL 60208

K. Kao, L. Keer

Northwestern University, Mechanical Engineering Department, 2145 Sheridan Road, Evanston, IL 60208

J. Electron. Packag 134(3), 031006 (Jul 18, 2012) (7 pages) doi:10.1115/1.4006708 History: Received September 30, 2011; Revised March 27, 2012; Published July 18, 2012; Online July 18, 2012

In displacement controlled mechanical fatigue of ball grid solder interconnect arrays, decrease in maximum load monitors total increase in crack area in an array while electrical resistance monitors only the area of large cracks that lead to electrical failure. Small cracks with good electrical contact between the crack surfaces have only minor effect on the resistance of the array. In this mechanical fatigue research of ball grid arrays, the fatigue damage was continually followed by simultaneously measuring maximum load and electrical resistance. Experimental details, results, and analysis of the results are given including a Paris relation fit to the data.

Copyright © 2012 by American Society of Mechanical Engineers
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Figure 1

Diagram of shear fatigue test apparatus with specimen

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Figure 2

Reflow temperature (°C) profile measured at the top of the components placed on the 23 mm board locations. The timescale is in minutes (from 0 to 6) and there are seven heating zones. This was measured 4 times. The top figure is a schematic of the daisy chain electrically connected array with 288 ball grid interconnections.

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Figure 3

Cross-section diagram of an individual interconnect with nominal dimensions shown

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Figure 4

(A) Photo of a fatigue test with real-time resistance data with the installed collection equipment. (B) Circuit diagram of in situ resistance measurement experiment.

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Figure 5

The monotonic shear stress versus shear strain response of a BGA sample containing 288 interconnects. All deformation from sources other than the interconnects were subtracted. The plot also shows real-time resistance versus total shear strain.

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Figure 6

Shows maximum shear stress and electrical resistance for each cycle near beginning and ending cycles. The shear stress does not give distinct signal of initial interconnect failure whereas real-time electrical resistance does.

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Figure 7

Calculated crack area propagation rates in a fatigue test. Three crack stages appear to be delineated. Although in stage II the crack rate decreases temporarily, these results may be interpreted to show the crack may have temporarily stopped at a void before final rapid propagation toward failure, or burnishing may have caused better electrical contact (reducing the resistance at crack surfaces).

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Figure 8

Crack area determined from maximum stress versus number of cycles. The change in maximum stress measures change in crack area for the total number of interconnects. Five zones of differing total crack propagation rates versus cycle number, labeled by numbers, are shown on the figure.

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Figure 9

The equivalent crack length was calculated using the resistivity data assuming a thumbnail shaped crack. A fit of the Paris’ law to the crack growth data gave da/dN = CK)m , C = 6.7 × 10− 20 and m = 2.25.




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