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Research Papers

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

[+] Author and Article Information
Jordan C. Roberts, Mohammad Motalab, Safina Hussain, Richard C. Jaeger, Pradeep Lall

Department of Mechanical Engineering, Department of Electrical and Computer Engineering, Center for Advanced Vehicle and Extreme Environment Electronics (CAVE3 ),  Auburn University, Auburn, AL 36849

Jeffrey C. Suhling

Department of Mechanical Engineering, Department of Electrical and Computer Engineering, Center for Advanced Vehicle and Extreme Environment Electronics (CAVE3 ),  Auburn University, Auburn, AL 36849jsuhling@eng.auburn.edu

J. Electron. Packag 134(3), 031005 (Jul 18, 2012) (17 pages) doi:10.1115/1.4006910 History: Received July 31, 2011; Revised May 11, 2012; Published July 18, 2012; Online July 18, 2012

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

Copyright © 2012 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Packaging architecture for a high performance flip chip microprocessor

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Figure 2

Piezoresistive sensor concept

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Figure 3

Optimized eight-element rosette on (111) silicon

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Figure 4

Area array flip chip stress test chip (20 × 20 mm, 3600 I/0)

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Figure 5

Array of identical 5 × 5 mm regions

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Figure 6

Wirebond stress test chip (JSE 200)

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Figure 7

Redistribution pattern on each 5 × 5 mm region

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Figure 8

Photograph of the sensor rosettes

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Figure 9

Measured piezoresistive coefficients

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Figure 10

Schematic of CLGA stress test chip assembly

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Figure 11

Ceramic flip chip LGA test assemblies and packaging process steps

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Figure 12

Test chip rosette sites for stress measurement and solder ball groups for electrical access

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Figure 13

X-ray verification of solder bumps

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Figure 14

CSAM verification of die-underfill interface

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Figure 15

Electrical connection via flex LGA socket

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Figure 16

Standard clamping of the LGA component

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Figure 17

Clamping fixture #1 for the ceramic LGA (based on heat sink design)

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Figure 18

Clamping fixture #2 for the ceramic LGA (after solder reflow and underfill steps)

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Figure 19

Clamping fixture #3 for the ceramic LGA (after lid attachment step)

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Figure 20

Manual probing of the ceramic LGA for clamping fixture verification

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Figure 21

Comparison of die stresses measured with the various clamping fixtures

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Figure 22

Clamping fixture used in heat sink experiments

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Figure 23

Thin force sensor

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Figure 24

Evolution of die stress at the center of the chip (compressive horizontal normal stress)

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Figure 25

Evolution of the six die stress components at the center of the chip

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Figure 26

Evolution of the six die stress components at the corner of the chip

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Figure 27

Multipoint constraint technique applied to different layers of the CLGA component

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Figure 28

Stress–strain curves of the ceramic substrate

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Figure 29

Underfill stress–strain curves

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Figure 30

Anand constants for modeling of SAC solder

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Figure 31

Quarter symmetry mesh for solder reflow model

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Figure 32

Layout of solder bumps

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Figure 33

Die stress buildup during cooldown after solder joint reflow

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Figure 34

In-plane normal stress σ11′ distribution after die attachment process

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Figure 35

In-plane normal stress σ22′ distribution after die attachment process

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Figure 36

Quarter symmetry mesh for underfill cure model

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Figure 37

In-plane normal stress σ11′ distribution after underfill curing process

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Figure 38

In-plane normal stress σ22′ distribution after underfill curing process

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Figure 39

Quarter symmetry mesh for lid attachment model

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Figure 40

TIM layer for lid attachment model

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Figure 41

In-plane normal stress σ11′ distribution after lid attachment and TIM1 curing process

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Figure 42

In-plane normal stress σ22′ distribution after lid attachment and TIM1 curing process

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Figure 43

Correlation of finite element predictions with stress sensor data (solder joint reflow)

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Figure 44

Correlation of finite element predictions with stress sensor data (after underfill cure)

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Figure 45

Correlation of finite element predictions with stress sensor data (after lid attachment)

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Figure 46

CBGA heat sink clamping geometry

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Figure 47

Die in-plane normal stress change at the center of the chip due to heat sink clamping force

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Figure 48

Die in-plane normal stress change at the corner of the chip due to heat sink clamping force

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Figure 49

Quarter symmetry mesh CBGA assembly

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Figure 50

Boundary conditions and loading for clamping finite element model

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Figure 51

Nonuniform pressure applied to the lid of the package during clamping measurements

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Figure 52

Die in-plane normal stress change at the center of the chip due to heat sink clamping force

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