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Research Papers

Parameter Calibrations on MOSFET Stress Sensors

[+] Author and Article Information
Ren-Tzung Tan, Hsien Chung, Chun-Pai Tang

Semiconductor Laboratory, Chung-Cheng Institute of Technology,  National Defense University, Ta-Shi, Tao-Yuan 33509, Taiwan, R.O.C

Ben-Je Lwo1

Semiconductor Laboratory, Chung-Cheng Institute of Technology,  National Defense University, Ta-Shi, Tao-Yuan 33509, Taiwan, R.O.Clwob@ndu.edu.tw

Kun-Fu Tseng

Department of Electronic Engineering, Asia-Pacific Institute of Creativity, Tao-Fan, Miao-Li 35153, Taiwan, R.O.C.kftseng@ms.apic.edu.tw

1

Corresponding author.

J. Electron. Packag 134(3), 031004 (Jul 18, 2012) (7 pages) doi:10.1115/1.4006888 History: Received July 27, 2011; Revised May 07, 2012; Published July 18, 2012; Online July 18, 2012

Due to the carrier mobility changes with the mechanical loading and its small size, the MOSFET (metal-oxide-semiconductor field-effective-transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging. In this work, a complete and accurate approach to calibrate the coefficients for both types of MOSFET stress sensors under thermal and mechanical loadings was investigated quantitatively. Through data from different measurement modes on different types of MOSFET, the optimal experimental methodology was next proposed for the sensor applications on packaging stress extraction. The thermomechanical coupling coefficients for the selected experimental mode were finally extracted so that packaging stress measurements with MOSFET under elevated temperature can be performed more accurately.

Copyright © 2012 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

The MOSFET directions (not on scale)

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Figure 2

Wafer strip preparation

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Figure 3

The ideal representation (left) and actual 4PB fixture (right)

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Figure 4

The experimental setup

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Figure 5

The ID –VD plots at different temperature for a typical (a) n-MOSFET and (b) p-MOSFET

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Figure 6

Plots extracted from data in Fig. 5 at different drain voltages

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Figure 7

The ID –VG plots at different temperature for a typical (a) n-MOSFET and (b) p-MOSFET

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Figure 8

Plots extracted from data in Fig. 7 at different gate voltages

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Figure 9

The ID –VD plots for a typical X-axis (a) n-MOSFET, (b) p-MOSFET

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Figure 10

The ID –VD results extracted from the data in Fig. 9 at different drain voltages

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Figure 11

The ID –VG plots for a typical X-axis (a) n-MOSFET, (b) p-MOSFET

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Figure 12

The ID –VG results extracted from the data in Fig. 1 at different gate voltages

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Figure 13

ID –VD plots extracted from Y-axis samples at different drain voltages

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Figure 14

Stress–current relationship for the typical p-type MOSFET devices at 90 °C

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Figure 15

The coupling effects extraction for p-MOSFET on (a) πx and (b) πy

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