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Research Papers

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

[+] Author and Article Information
Kota Nakahira

Department of Nanomechanics, Graduate School of Engineering,  Tohoku University, 6-6-11-716, Aoba Aramaki, Aobaku, Sendai, Miyagi 980-8579, Japankota.nakahira@rift.mech.tohoku.ac.jp

Hironori Tago, Fumiaki Endo

Department of Nanomechanics, Graduate School of Engineering,  Tohoku University, 6-6-11-716, Aoba Aramaki, Aobaku, Sendai, Miyagi 980-8579, Japan

Ken Suzuki

Fracture and Reliability Research Institute, Graduate School of Engineering,  Tohoku University, 6-6-11-716, Aoba Aramaki, Aobaku, Sendai, Miyagi 980-8579, Japan

Hideo Miura1

Fracture and Reliability Research Institute, Graduate School of Engineering,  Tohoku University, 6-6-11-716, Aoba Aramaki, Aobaku, Sendai, Miyagi 980-8579, Japanhmiura@rift.mech.tohoku.ac.jp

1

Corresponding author.

J. Electron. Packag 134(2), 021006 (Jun 11, 2012) (6 pages) doi:10.1115/1.4006142 History: Received August 24, 2011; Revised February 10, 2012; Published June 11, 2012; Online June 11, 2012

Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

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Copyright © 2012 by American Society of Mechanical Engineers
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Figures

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Figure 1

Three-dimensional finite element model for analysis of residual stress in a Si chip mounted on the area-arrayed fine bumps

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Figure 2

Change of the stress-strain curve of the electroplated copper thin films as a function of the annealing temperature

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Figure 3

Dynamic and thermo mechanical analyses of test underfill materials (a) Temperature dependence of Young’s modulus, (b) Temperature dependence of elongation

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Figure 4

Local distribution of the residual normal stress on the silicon chip surface (a) Bump pitch: 400 μm, (b) Bump pitch: 600 μm

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Figure 5

Change of the local distribution of the residual normal stress on the silicon chip surface as a function of Young’s modulus of the electroplated copper bumps

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Figure 6

Structural variation of the position of a bump with respect to the position of the via in the interconnection on a silicon chip (a) TSV on a bump, (b) TSV on underfill

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Figure 7

Effect of the relative position between bumps and vias on the residual stress in the mounted chip

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Figure 8

Test substrate for measuring the local deformation and residual stress of a silicon chip (a) Test substrates with area-arrayed bumps, (b) Electroplated tin/copper bump

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Figure 9

Stress sensing chip with embedded strain gauges (a) Stress-sensing chip, (b) Strain gauges formed on a (001) crystallographic plane of silicon

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Figure 10

Example of the local deformation of a silicon chip mounted on the area-arrayed bumps (Bump pitch: 400 μm)

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Figure 11

Outlook of the back surface of a silicon chip mounted on the area-arrayed bumps

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Figure 12

Effect of bump pitch and mechanical properties of underfill on the local deformation of a silicon chip

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Figure 13

Local distribution of the residual stress between two bumps (a) Bump pitch: 400 μm, (b) Bump pitch: 400 μm

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