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Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages OPEN ACCESS

[+] Author and Article Information
P. Tumne1

V. Venkatadri, D. Santos, R. Havens, K. Srihari

Department of Systems Science and Industrial Engineering,  Binghamton University, Binghamton, NY 13902-6000

S. Kudtarkar, M. Delaus

Analog Devices, Inc., Wilmington, MA 01887

1

Corresponding author.

J. Electron. Packag 134(2), 020905 (Jun 11, 2012) (7 pages) doi:10.1115/1.4005906 History: Received July 31, 2011; Revised November 15, 2011; Published June 11, 2012; Online June 11, 2012

Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

The semiconductor industry has transitioned from various conventional packages to WLCSP in the recent years. The main advantage of WLCSP technology is saving the “real estate,” which is crucial in acquiring a space, primarily in the portable consumer market. The products in this market space are more susceptible to mechanical loading than thermomechanical type of failure. Hence, this market space demands the solder joints to have the ability to sustain mechanical loading. This kind of solder joint reliability is characterized by board level drop test [1-5].

WLCSP is assembled at the wafer level and could potentially have the following design variations:
  • direct bump versus RDL process
  • use of backside lamination
  • bond pad stack-up variations
  • different lead (Pb) free solder compositions
  • total package height
  • UBM, thickness, and deposition methods

Further, these packages in most end-user applications are mounted on boards without underfill. This research paper considers all of these aforementioned parameters and studies their effect on the solder joint integrity. The study, in this paper, is restricted to the mechanical shock type of failures, hence using board level drop test. Both, analytical and statistical approaches are used to study the effects of mechanical loading on the solder joints.

WLCSPs were mounted on Joint Electron Devices Engineering Council (JEDEC) standard drop test boards by standard surface mounting procedure. JEDEC boards have multilayer buildup technology (1 + 6 + 1) stack-up and are double sided with a via in pad (primary side) and no via in pad (secondary side). Further, each side can accommodate 15 components of the same type in three rows with five column format [6]. All the test results reported in this paper were conducted on the no via in pad (secondary side). The test condition used was JESD22-B111–1500 g, 0.5 ms. The sample size was four boards (60 test vehicles) per “leg.” The drop test was conducted until each board recorded 80% (12 or more failures), and the failure criterion was intermittent discontinuity of resistance greater than 1000 Ω lasting for 1 μs or longer for three successive events. The different legs used for this research work are summarized in Table 1.

In reliability prediction of drop or shock type oftesting, Weibull distribution is widely used in the industry. It may have been a good statistical fit for Pb based alloys, but it fails to provide a good fit for Pb free solder alloys and does not match with the physical significance due to the complexity in the failure modes and mechanisms [7]. Furthermore, such prediction methodology may lead to unrealistic deviation from the true reliability estimates and may overestimate or underestimate the reliability. Another approach for the data analysis is using the grouped and ungrouped methods to make conclusion on the reliability estimates. In grouped data analysis, data are grouped in different classes as the total number of components failed within that class. In ungrouped type of data analysis, the data are used as a direct observation of the number of drops to failure [8]. Even in the grouped and ungrouped type of data analyses, the observation was that the reliability predictions could varywhen using multiply censored data [9]. However, in the current research, the data used were singly censored (right censored), because the test was terminated after reaching 80% failures.

Brittle fracture failure mode is dominant in drop testing [10]. In such cases, use of Neville distribution is supported by physical evidence of the brittle failures [11-13]. In this current work, Neville distribution was fitted to all ten legs of right censored drop test data. The probability of failure of a component within 30 drops of failure (criteria as per JESD22-B11 standard) was estimated using the cumulative distribution function of Neville distribution fitted for all the ten legs. These probabilities were used to estimate the parts per million (PPM) levels of each leg.

Each leg in the test matrix passed minimum JEDEC standard requirement of no failures until 30 drops. Both, grouped and ungrouped data analyses were conducted on all ten legs. Equation and procedure for the grouped and ungrouped data analyses are described elsewhere [14]. For singly censored data, there were no significant differences in the reliability estimates between the grouped and ungrouped data (see Fig. 1). Since grouped data were slightly conservative, they were used for comparison and reliability prediction throughout the paper. The drop test results are plotted using reliability (Ri) on y-axis and number of drops to failure on the abscissas. Each of the design parameters is discussed separately and corresponding legs are compared.

Effect of Solder Alloy.

Sn-Ag-Cu solder alloys with varying percentage of Ag were used in this study. Figure 2 shows the comparison between SAC 105 and SAC 266 for a 9 × 9 direct array with similar design. Components with lower Ag content (SAC 105) sustained more drops. In Fig. 2, a comparison between the low and high Ag contents (SAC 105 and SAC 405) on the 10 × 10 RDL array size shows that SAC 105 has performed better than SAC 405. Comparing the results for different array sizes (9 × 9 and 10 × 10), from Figs. 2 and 2, it is very clear that solder alloy with lower Ag content performed better irrespective of the array size and attach method (direct versus RDL).

Effect of Pitch and Package Height.

Pad pitch varied at two levels (0.4 mm and 0.5 mm). Along with pad pitch, the package height also varied. For 0.4 mm pitch, the package height was 500 μm, whereas for 0.5 mm pitch it was 600 μm. Package height of 600 μm has a silicon die with greater thickness than that for 500 μm package height. Thin silicon provided a better drop performance than thick silicon. Figure 3 shows an increase in the pad pitch and package height, which led to significant reduction in number of drops to failures.

Effect of Array Size.

Various array sizes such as 8 × 8, 9 × 9, and 10 × 10 were used in this study. Comparison was made when there was minimal variation in the design parameters between the legs for two different array sizes. Figure 4 shows comparison between 9 × 9 and 10 × 10. Smaller array size (9 × 9) shows better performance than larger array size (10 × 10). The stress observed in the outermost solder joint is greater in a 10 × 10 array compared to a 9 × 9 array due to the larger distance from neutral point for a 10 × 10 array.

Effect of WLCSP Type.

In this case, the effect of WLCSP type was studied at two different pitches and package heights. It was found that at a 0.5 mm pitch and package height of 600 μm, RDL shows better performance than direct type of design. Direct type of design on the 0.5 mm pitch and package height of 600 μm has a steeper reliability curve indicating large number of failures in short time intervals as shown in Fig. 5. Further, this difference is less pronounced when similar comparison is made at a pitch of 0.4 mm with a package height of 500 μm between direct and RDL attach methods. Figure 5 shows that the reliability curves are not significantly different.

Effect of UBM Thickness.

In this research, UBM deposition methods used were sputtered and plated types. Another difference within these legs is the backside laminate coat thickness. Plated UBM has thin backside laminate; on the other hand, sputtered UBM has a thick backside laminate. Plated UBM has higher reliability than sputtered UBM despite that plated UBM has 3.9% Ag and sputtered UBM has 2.6% Ag content in the alloy as shown in Fig. 6. This indicates that the type of UBM deposition method used in the WLCSP can significantly affect the drop performance. Small array size, and twice-thick overall plated UBM than sputtered UBM, possibly increased the performance. This further indicates that at higher silver percentage, the type of UBM deposition method is a significant factor that can affect the drop test performance.

Effect of Board Thickness.

Two different board thicknesses were evaluated. Thinner board (0.8 mm) showed better performance than thicker board (1 mm) (see Fig. 7). Another difference between these two legs was the package height. Thicker board had larger package height of 600 μm, whereas thinner board had a package height of 500 μm. This further confirms that thin silicon helps in increasing the drop performance. Less number of components failed on the thinner board, while others have been censored and hence reliability curve stops between 600 and 800 drops, whereas for thicker board the number of failures increased as the drops increased.

In drop testing, failures were detected by in situ resistance monitoring using an event detector and further analyzed by mechanical polishing of components at failed locations. Different design configurations have failure modes within and near the component side of the solder joint. Since silicon is more rigid than the printed circuit board (PCB) board, it is common in mechanical shock type of asymmetric loading that the bump region near silicon will face larger stress than that on the PCB side [14]. In the case of comparison between the effects of the solder alloy composition, the lower silver percentage alloy showed better drop performance than higher silver percentage. This observation can be attributed to the fact that lower silver percentage alloy is softer [15-16] and has lower elastic modulus [17]. In comparison between SAC 105 and SAC 405, the type of intermetallic formed could be regarded similar due to same UBM and thickness. However, presence of greater silver percentage makes the alloy stiffer and hence exerts more stress in the intermetallic region [15-16]. Hence, the failure mode observed is the separation between the intermetallic and UBM region (see Fig. 8—Leg 9 with SAC 405 solder alloy) whereas in SAC 105 solder alloy, the failure mode is in the region near to intermetallic and partially through the bulk solder (see Fig. 9). The crack observed in the bulk region extends as the board is dropped until 80% of the components on that board have failed. Further, when SAC 105 was compared with SAC 266 on sputtered type of UBM, the failure location was partially confined to the intermetallic region for lower silver percentage alloy and complete intermetallic separation for higher silver percentage (see Fig. 1). Thus, as the silver percentage increases from 1% to 4%, the failure location shifted from partial bulk to separation in the UBM and interface.

The pitch and package height variation have shown transition in failure modes as well. Components with 0.4 mm pitch and package height of 500 μm showed separation between the plated UBM and bond pad metal (Fig. 1), whereas components with 0.5 mm pitch and 600 μm height had failures occurring on the side traces of the PCB (Fig. 1). Thus, shift in the maximum stress location is due to change in the geometry. Moreover, PCB trace cracks occurred earlier than UBM separation, which indicates that UBM to bond pad adhesion could resist greater stress before separation.

Further, the type of WLCSP has shown varying results at different pitch conditions and UBM deposition methods. Direct type with plated UBM has shown transition in failure mode to trace cracking on the PCB side as seen in Fig. 1, whereas in RDL with plated UBM has shown to have failures in the RDL on the components side as shown in Fig. 1. Similar type of failure mode was seen in the RDL type WLCSPs with plated UBM when moving from 0.5 mm to 0.4 mm pitch. However, Direct and RDL types with sputtered UBM have shown to produce only interfacial failures at the component side. Thus, type of UBM deposition method and its thickness shifts the stress locations, in which case RDL with plated UBM can withstand larger number of drops to failure than other configurations. Another observation related to the type of plating can be seen by comparing Figs.  1112. Components with sputtered UBM tend to have crack path through the intermetallic at the component side, whereas for plated UBM the separation mode shifts between the UBM and the bond pad. This can be attributed to greater thickness of plated UBM as compared to sputtered UBM.

Board thickness has also shown an effect on the drop testing results. Comparison with the components for different board thicknesses showed that thinner boards lasted longer; however, the failure modes are similar as shown in Figs.  1516. Finally, array size also affects the drop performance, due to the increase in the distance from neutral point, the outermost solder joint experiences greater stress in larger arrays than in smaller one. Comparisons between 9 × 9 mm and 10 × 10 mm components from Figs.  1615, respectively, show that the failure modes were similar, i.e., separation between the intermetallic region and UBM.

To make overall comparison between all the legs used in this study, Neville distribution was used to model the actual failure data in terms of number of drops to failure. For all ten legs, Neville distribution showed a good fit for the right censored data when compared to the Weibull distribution data (see Figs. 1 and 1). Shape and scale parameters of the fitted Neville distribution were estimated for all ten legs. Based on the shape and scale parameters, the PPM levels were calculated, which give the estimate of number of components, which will fail, in million parts tested before 30 drops. The shape and scale parameters of all ten legs are summarized in Table 2. Lower the PPM value better will be the design combination to sustain mechanical shock. Leg 6 shows the lowest PPM value and leg 7 shows the highest PPM value.

Drop test was performed on WLCSPs to analyze the effect of various design parameters. Grouped data analysis on the right censored type data has shown better reliability estimates. The results obtained from the Neville distribution to fit the data and the PPM values calculated are in conformance with the results obtained from grouped data reliability curve. Design variables in WLCSPs have shown significant effect on the drop performance. The results are summarized in Table 3 and explained below:
  • Smaller array size was better; this can be attributed to less distance from neutral point.
  • Low Ag content alloy showed better performance. Increase in silver percentage showed transition in failure mode from partial bulk to complete intermetallic separation.
  • Smaller pitch and package heights had shown better reliability.
  • WLCSPs with RDL at 0.5 mm pitch have better reliability when compared to direct WLCSP. However, this difference is less significant when the pitch is reduced from 0.5 to 0.4 mm.
  • Plated UBM has shown good drop test results, even with higher Ag content of 3.9% as compared to sputtered UBM with lower Ag content of 2.6%.
  • Variation in the failure modes was observed for different design configurations. Direct and RDL types of attach with sputtered UBM have consistently shown intermetallic cracking irrespective of the solder alloy composition. But direct type attach with plated UBM showed trace cracking at board side, and RDL cracking was seen in RDL and plated type of UBM.
  • For comparison between different board thicknesses, smaller package height had consistently shown better performance.
  • Solder alloy composition has stronger effect on the drop test performance than the other design parameters.

This research effort investigated various design parameters in WLCSPs with respect to drop test performance. Due to greater number of parameters and limited experimental runs, only main effects could be studied. However, these results do provide an indication that there are possible interactions, which will be explored in future along with additional design parameters such as variation in the repassivation thickness and material.

The authors would like to thank Dr. Kathy O`Donnell, Steven Natale, and Justin Nyguen for their valuable help in conducting the drop tests and mechanical cross-sections.

Copyright © 2012 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Grouped versus ungrouped data analysis

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Figure 2

Effects of solder alloy: (a) leg 5 versus leg 6—SAC 266 versus SAC 105 and (b) leg 8 versus leg 9—SAC 105 versus SAC 405

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Figure 3

Effect of pad pitch and package height (leg 1 versus leg 3—0.5 mm pitch versus 0.4 mm)

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Figure 4

Effect of array size (leg 7 versus leg 10—10 × 10 versus 9 × 9 array)

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Figure 5

Effects of WLCSP type: (a) leg 1 versus leg 2—Direct versus RDL for 0.5 mm pitch and (b) leg 3 versus leg 4—Direct versus RDL for 0.4 mm pitch

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Figure 6

Effect of UBM and top metal thickness (leg 1 versus leg 5—plated UBM with standard top metal versus sputtered UBM with thick top metal)

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Figure 7

Effect of board thickness (leg 7 versus leg 9—0.8 mm versus 1.0 mm)

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Figure 8

Separation between intermetallic and UBM in SAC 405 on RDL at 200 × (leg 9)

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Figure 9

Partial bulk and intermetallic failure in SAC 105 on RDL at 200 × (leg 8)

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Figure 10

Complete intermetallic failure in SAC105 at 200 × (leg 6—Direct type with sputtered UBM)

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Figure 11

Complete separation in intermetallic in SAC 266 at 200 × (leg 5—Direct type with sputtered UBM)

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Figure 12

Separation between UBM and bond pad for 0.4 mm pitch and 500 μm package height at 1000 × (leg 3)

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Figure 13

Trace crack on the board side for 0.5 mm pitch and 600 μm package height at 200 × (leg 1)

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Figure 14

Crack in the RDL layer with plated UBM at 1000 × (legs 2 and 4)

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Figure 15

Separation between intermetallic and UBM for 0.8 mm thick board with 10 × 10 array at 400 × (leg 7)

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Figure 16

Separation between intermetallic and UBM for 0.8 mm board with 9 × 9 array at 400 × (leg 10)

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Figure 17

Probability plots for: (a) Neville distribution (leg 9) and (b) Weibull distribution (leg 9)

Tables

Table Grahic Jump Location
Table 1
Design test matrix
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Table 2
PPM calculation using Neville Distribution
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Table 3
Effect of design parameters on drop test performance of WLCSP—summary

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