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Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package OPEN ACCESS

[+] Author and Article Information
Takahiro Kinoshita, Takashi Kawakami, Tatsuhiro Hori

 Toyama Prefectural University, Department of Mechanical Systems Engineering, Kurokawa, Toyama, 939-0398, Japan

Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada

 Association of Super-Advanced Electronics Technologies, Shinkawa, Tokyo, 104-0033, Japan

J. Electron. Packag 134(2), 020903 (Jun 11, 2012) (4 pages) doi:10.1115/1.4006515 History: Received July 27, 2011; Revised February 04, 2012; Published June 11, 2012; Online June 11, 2012

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

FIGURES IN THIS ARTICLE
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Recently, the high density 3D packaging technology has been developed to reduce the size and to improve the performance of semiconductor devices [1-7]. TSV technique has enabled faster electrical-signal transfer between semiconductor chips. The transmission delay time of signals, which depends on circuit lengths, is lower for 3D packaging structures as compared to the existing 2D packaging structures. Due to the above advantages, 3D SiP with TSV technique has been widely investigated for cooling systems, manufacturing systems, and device designs. However, the methods and tools to estimate the mechanical stresses generated in 3D SiP structures are still under development.

The cross-section of a 3D stacked structure is shown in Fig. 1. The TSVs in this system are arranged in full area array configuration. The structure was developed by Association of Super-Advanced Electronics Technology (ASET) [8]. In complex device structures such as the one shown in Fig. 1, the thermal stresses generated in the systems are mainly caused by the mismatch of coefficients of thermal expansion (CTE) and temperature variations of the materials constituting the systems.

There have been several reports on 3D device fabrication that some voids are formed in solder bump, underfill, and TSVs. These voids are the potential factors for initiations and propagations of cracks and lowering the fatigue life time of integrated materials. Experimental and computational studies on the effects of void have been previously performed to ensure the reliability of electronics devices [9-13].

In this study, the effects of the presence of voids inside the TSVs in a 3D SiP structure on the thermal conduction and the thermal stresses in the TSV structure under device operating condition are analyzed using the large scale simulator, ADVENTURECluster® . The thermal performance of the TSVs required in order to keep the device temperature under its maximum allowed value, and the mechanical stresses in the Cu TSVs and in the Si chips are obtained from the simulations.

Simulation Model and Dimensions.

The schemes of one chip model (one chip and one column) with the TSV structure without and with a void in the TSV structure were shown in Fig. 2. Periodic boundary conditions were assumed for both models. The model consists of a TSV (Cu), a microbump (Cu), a semiconductor chip (Si), an insulator layer (SiO2 ), a nitride layer (SiN), and an underfill resin. The void was modeled as a spheroid and was arranged at the center part of the TSV. Material properties used in this study were shown in Table 1.

The dimensions of the simulation model were shown in Fig. 3. The width of the model along the X and Y axes were 50 μm due to the pitch of the square arrangement of the TSVs. The height was 83 μm along the Z direction. The diameter of the TSV was 25 μm. The thickness of the insulator was 1 μm and it was arranged between the TSV and the Si chip. The thickness of the nitride layer was 1 μm. The diameter of the microbump was 30 μm and its height was 6 μm. Microbump was surrounded by underfill resin. For the model with a void inside the TSV, the length of the major axis and minor axis of the spheroid void were 20 and 10 μm, respectively.

FEM Model.

The FEM model without void was shown in Fig. 4. The model was built by importing the CAD data to the FEM simulator, ADVENTURECluster [14]. In this study, all the materials were modeled by Pro/Engineer (wild fire 3.0 version).

In building the FEM model, the mesh for thin layer materials with 1 μm thickness was generated by two layers along the thickness direction to avoid generations of numerical discontinuities for temperature and stresses. The distance between elementary nodes was 0.5 μm. Quadratic tetrahedral element was adopted in this study. In the case of the TSV structure without void, the number of elements and the degree of freedom (DOF) for the model were 1,171,132 and 6,070,365, respectively. In the case of the TSV structure with a void, number of elements and DOF of the model were 1,171,596 and 6,068,577, respectively.

Thermal Conductive Simulation.

In this study, a steady-state thermal conductive simulation was carried out to estimate the required cooling performance of the model.

Heat transfer coefficient was applied on the top and the bottom planes of the FEM model for cooling. A heat flux of 5 W/cm2 was applied on the bottom plane of Si chip as a heat-generator. The heat transfer coefficient for the bottom plane of FEM model was assumed to be 5 W/m2 K as naturally cooling. The heat transfer coefficient applied on the top plane of FEM model was varied as 500, 700, and 900 W/m2 K. In each case, the maximum temperature of the model was estimated and a linear interpolation was conducted.

Lateral faces, the X and Y planes, were assumed to be adiabatic surfaces because of the periodic boundary condition of the model. The reference temperature was taken to be room temperature (25 °C).

The required heat transfer coefficient for the device was estimated by linear interpolation for the case where the maximum temperature of the model corresponded to the maximum device operating temperature which is 85 °C in our case.

For the case without void inside the TSV, the same procedures were carried out to estimate the maximum temperatures and to conduct the linear interpolation.

Thermal Stress Simulation.

In this study, an elastic thermal stress simulation was carried out to discuss the effect of the presence of void inside the TSVs on the stresses in the TSV structures including the Cu TSV and the Si chip under the device operating condition. The temperature distribution of the model was obtained in advance by thermal conductive simulation. The distribution obtained was adopted to estimate the thermal stresses which depend on temperature elevation. The stress free temperature was assumed to be the room temperature of 25 °C, which corresponds to the power OFF state of the devices.

Semiconductor chip has a number of TSVs in inner planes and the TSVs are built in square arrangement along X and Y axes direction. Lateral faces, X and Y planes, are constrained by keeping flat and by not rotating along the Z axis direction due to periodic boundary of the model along the X and Y axes direction.

In the steady-state thermal conductive simulation, a one chip model without voids inside the TSV was adopted, and the heat generation was given to be 5 W/cm2 at the bottom plane of the Si chip. The required heat transfer coefficient for the model was estimated to be 680 W/m2 K from the relation between the heat transfer coefficient and the maximum temperature in the model. In the case of the model with a void inside the TSV, the same heat transfer coefficient was estimated. In the case of the simulation with the above required heat transfer coefficient, the maximum temperature of the device was close to 85 °C and almost uniform temperature distribution was estimated in both the models with and without a void in the TSVs.

The results of the elastic thermal stress simulation, the equivalent stress distributions in the cross-sections of the models without and with a void inside the TSVs were shown in Fig. 5. In the case of the TSV structure without voids, the stresses in the Cu TSVs were close to the hydrostatic pressure because the equivalent stress has been estimated to be about 40 MPa. The magnitude of the equivalent stress was lower than the yield stress of bulk copper which is 230 MPa.

It was insisted that TSV was not broken by fatigue under thermal cycle condition due to power ON/OFF of device. In case of the TSV structure with a void, the stress concentration was occurred around the void inside the TSV and the magnitude of the equivalent stress was about 120 MPa. It was larger than the stress obtained for the case of the TSV structure without voids, but it was also lower than the yield stress of the bulk copper. It was also insisted that TSV was not broken by fatigue under thermal cycle condition due to power ON/OFF of device.

Maximum principal stress distributions in the cross-section of one chip model without voids and with a void were shown in Fig. 6. The TSV and the SiO2 insulator layers were removed in the figure and only the cylindrical inner surfaces of Si were shown. In the case of the TSV structure without voids, the stress on inner surface of Si was estimated to be about 90 MPa. Its stress level should not be negligible for the crack generation in Si chips. In the case of the TSV structure with a void, the stress was estimated to be about 85 MPa. The maximum principal stress on the inner surface of Si was slightly reduced by the existence of a void in the TSV. However, the stress level should not be also negligible for crack generations in Si chips.

In this study, the feasibility of thermal conduction and mechanical stress analyses for a TSV structure including the TSVs and Si chips in 3D SiP was discussed with a large scale simulator based on FEM to ensure the reliability of electronics devices for the cases of the TSV structures without voids and with a void inside the TSVs.

In the results of the steady-state thermal conductive simulation, the required heat transfer coefficient for keeping the device temperature under the maximum allowed operating temperature was quantitatively estimated to be 680 W/m2 K for the system studied when the heat generation of the device was assumed to be 5 W/cm2 in the chip.

In the results of elastic thermal stress simulation, it was shown that the TSV was not broken by fatigue under thermal cycle condition due to the power ON/OFF of the device. However, the maximum principal stress was estimated to be about 90 MPa on the inner surfaces of Si chip. It suggested that the stress level should not be negligible for damages in TSVs and Si chips.

This work was entrusted by NEDO “Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology” Project that is based on the Japanese government’s METI “IT Innovation Program.”

Copyright © 2012 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Cross-section of 3D stacked structure and its enlarged figure around TSV (courtesy of ASET)

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Figure 2

Scheme of one chip model of the TSV structure without void (left) and with void (right)

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Figure 3

Dimensions of one chip model without void

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Figure 4

FEM model for one chip model without void

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Figure 5

Equivalent stress distribution of one chip model without void in TSV (left) and with void in TSV (right)

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Figure 6

Maximum principal stress distribution of one chip model without void in TSV (left) and with void in TSV (right)

Tables

Table Grahic Jump Location
Table 1
Material properties

Errata

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