Research Papers

Thermal Modeling Technique for Multiple Transistors Within Silicon Chip

[+] Author and Article Information
Tohru Suwa

Associate Professor Japanese Associate Degree Program,  Universiti Selangor, Jln Zirkon A7/A, Seksyen 7, 40000 Shah Alam, Selangor, Malaysiasuwa@shibaura-it.ac.jp

Hamid Hadim

Professor Department of Mechanical Engineering,  Stevens Institute of Technology, Castle Point on Hudson, Hoboken, NJ 07030Hamid.Hadim@stevens.edu

J. Electron. Packag 133(4), 041015 (Dec 23, 2011) (7 pages) doi:10.1115/1.4005291 History: Received September 14, 2010; Revised August 23, 2011; Published December 23, 2011; Online December 23, 2011

Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. Sharp temperature increases within small areas, which are called “hot spots”, often occur in silicon chips. For more efficient designs, the temperature and location of hot spots need to be predicted with acceptable accuracy. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis of silicon chips at micrometer level has not been possible using conventional techniques. In the present study, an efficient and accurate multi-level thermal modeling and analysis technique has been developed. The technique combines finite element analysis sub-modeling and a superposition method for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained by superimposing the finite element analysis result. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled using the finite element method, the effect of the package and its boundary conditions are also included in the superposition results, which makes it possible to model a large number of transistors on a silicon chip. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip with 4 × 106 transistors.

Copyright © 2011 by American Society of Mechanical Engineers
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Figure 1

Typical standard cell packaging hierarchy

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Figure 2

Global- and sub-finite element models

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Figure 3

Illustrative example of superposition method with three heat sources

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Figure 4

Superposition model validation results

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Figure 5

Heat generation used in transistor temperature prediction

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Figure 6

Temperature rise distribution within silicon chip obtained by superposition method

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Figure 7

Temperature contour comparison between different number of transistor gate cases

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Figure 8

Maximum silicon chip temperature with different number of transistors and same logic block heat generation

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Figure 9

Calculation time as function of number of transistor gates




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