0
Research Papers

A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems

[+] Author and Article Information
Vikram Venkatadri1

 Department of Systems Science and Industrial Engineering, Binghamton University,Binghamton, NY 13902-6000 vvenkat2@binghamton.edu

Bahgat Sammakia

 Department of Mechanical Engineering, Binghamton University, Binghamton, NY 13902-6000

Krishnaswami Srihari, Daryl Santos

 Department of Systems Science and Industrial Engineering, Binghamton University,Binghamton, NY 13902-6000

1

Corresponding author.

J. Electron. Packag 133(4), 041011 (Dec 09, 2011) (15 pages) doi:10.1115/1.4005298 History: Received June 04, 2010; Revised July 18, 2011; Published December 09, 2011; Online December 09, 2011

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

Copyright © 2011 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Figure 1

Integration levels and approaches [4]

Grahic Jump Location
Figure 2

Existing packaging and 3D integration technologies: (a) stacking of fully packaged die (b) die stacking based on wire bonding, (c) die stacking using wireless interconnection, (d) die stacking using controlled collapse chip connection (C4) bumps and TSVs, (e) die stacking based on thin-film bonding, and (f) monolithic 3D approach [6]

Grahic Jump Location
Figure 3

Wafer level thin chip integration approach [7]

Grahic Jump Location
Figure 4

Ultra thin chip embedded in polymer [8]

Grahic Jump Location
Figure 5

Challenges in 3D integration

Grahic Jump Location
Figure 6

(a) Loop thermosyphon and (b) HP Vectra PC with the thermosyphon assembly [26]

Grahic Jump Location
Figure 7

(a) Miniature loop heat pipe principle and (b) general view of miniature loop heat pipe [27]

Grahic Jump Location
Figure 8

(a) Schematic and (b) image of an electro-osmotic pump [28]

Grahic Jump Location
Figure 9

(a) Schematic and (b) close-up picture of the impinging jet cooling system [30]

Grahic Jump Location
Figure 10

(a) Schematic and (b) actual setup of a miniature vapor compression heat pump microelectronics cooling solution [33]

Grahic Jump Location
Figure 11

Schematic of miniature absorption heat pump microelectronics cooling solution [34]

Grahic Jump Location
Figure 12

Thermal management in 3D chip stacks using conventional air cooling [55]

Grahic Jump Location
Figure 13

Thermal management strategies in 3D stacks

Grahic Jump Location
Figure 14

Schematic of integrated liquid cooling system for 3D system using microfluidic channel [56]

Grahic Jump Location
Figure 15

Assembly of 3D prototype of integrated microfluidic channel cooling solution [58]

Grahic Jump Location
Figure 16

(a) Heat sink assembly showing the synthetic jet module and the chip stack cavity, (b) original heat sink with longitudinal air flow, and (c) modified heat sink with lateral air flow [60]

Grahic Jump Location
Figure 17

(a) 3D stack enclosure connected to a cylindrical finned heat sink, (b) heat sink assembly showing the synthetic jet module and the chip stack cavity, and (c) jet induced flow between the fins [61]

Grahic Jump Location
Figure 18

(a) Unidirectional cascade TEM and (b) multidimensional heat transfer system (MHTS) using TEM [62]

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In