Research Papers

Impact of Printed Circuit Board Via and Micro-Via Structures on Component Thermal Performances

[+] Author and Article Information
Valentin Bissuel, Michel Brizoux, Arnaud Grivon, Eric Monier-Vinard, Fabrice Pires

 Thales Corporate Services, 18, avenue du Marechal Juin, 92366 Meudon La Foret Cedex–France

J. Electron. Packag 133(3), 031013 (Sep 30, 2011) (8 pages) doi:10.1115/1.4004830 History: Received November 22, 2010; Revised August 02, 2011; Published September 30, 2011; Online September 30, 2011

Latest electronic component package types are pushing the need to more efficiently remove the dissipated heat using optimized thermal paths going through the printed circuit board (PCB) to reach PCB inner thermal planes. So, to optimize board cooling, the designer has more and more to deal with PCB architecture including high density interconnect (HDI) technology, which relies on small diameter laser drilled micro-vias. Compared with conventional PCB technologies, HDI creates denser interconnect substrates, containing multilevel micro-via structures that play a decisive role in the miniaturization of circuit boards but will exacerbate the component cooling design complexity. To improve the understanding of conventional and future configurations of via structure and their influence on the component thermal performances, a study was leaded on an micro lead frame package, which is now mainstream for both analog and digital functions. For still air conditions, the thermal simulation results show that via and micro-via structures allow to drain more than 90% of the component power through the PCB metallic planes and are mandatory to limit the temperature excess. Thus, the thermal modeling of the latest 3D Integrated Circuit is reinforcing the need to simulate in more thin details its board surrounding architecture as well as its packaging. However, a fine detailed modeling of board layers layout always exceeds the simulation tool capabilities and requires new modeling methodologies able to define the most significant thermal model. Based on DEvelopment of Libraries of PHysIcal models (DELPHI) methodology, the creation of a compact thermal model, compliant to a set of boundary conditions was investigated for a local board area. The thermal behavior prediction, found to be within ± 5% of error, demonstrates the feasibility of extending the boundary condition independence principle to board modeling in order to achieve a more efficient and accurate board cooling optimization.

Copyright © 2011 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.



Grahic Jump Location
Figure 1

Process flow for determining the most compliant DELPHI type thermal network

Grahic Jump Location
Figure 2

ΔTN = J,BC results for the 49 boundary condition cases

Grahic Jump Location
Figure 3

Standardized board dedicated to IC thermal performances comparison

Grahic Jump Location
Figure 4

Two Pyramid Stacked Chips in MLF48 package

Grahic Jump Location
Figure 5

Via in pad thermal enhancement for MLF48 cooling

Grahic Jump Location
Figure 6

Design of HDI 3 + 6 + 3 structures

Grahic Jump Location
Figure 7

Cross-section of a typical partially filled and fully filled micro-via

Grahic Jump Location
Figure 8

Improvement of HDI layers heat paths

Grahic Jump Location
Figure 9

Architecture using 16 micro-vias and 25 buried vias

Grahic Jump Location
Figure 10

Domain of board CTM model on an architecture using 25 filled micro-vias and buried vias




Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In