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Research Papers

Impact of Printed Circuit Board Via and Micro-Via Structures on Component Thermal Performances

[+] Author and Article Information
Valentin Bissuel, Michel Brizoux, Arnaud Grivon, Eric Monier-Vinard, Fabrice Pires

 Thales Corporate Services, 18, avenue du Marechal Juin, 92366 Meudon La Foret Cedex–France

J. Electron. Packag 133(3), 031013 (Sep 30, 2011) (8 pages) doi:10.1115/1.4004830 History: Received November 22, 2010; Revised August 02, 2011; Published September 30, 2011; Online September 30, 2011

Latest electronic component package types are pushing the need to more efficiently remove the dissipated heat using optimized thermal paths going through the printed circuit board (PCB) to reach PCB inner thermal planes. So, to optimize board cooling, the designer has more and more to deal with PCB architecture including high density interconnect (HDI) technology, which relies on small diameter laser drilled micro-vias. Compared with conventional PCB technologies, HDI creates denser interconnect substrates, containing multilevel micro-via structures that play a decisive role in the miniaturization of circuit boards but will exacerbate the component cooling design complexity. To improve the understanding of conventional and future configurations of via structure and their influence on the component thermal performances, a study was leaded on an micro lead frame package, which is now mainstream for both analog and digital functions. For still air conditions, the thermal simulation results show that via and micro-via structures allow to drain more than 90% of the component power through the PCB metallic planes and are mandatory to limit the temperature excess. Thus, the thermal modeling of the latest 3D Integrated Circuit is reinforcing the need to simulate in more thin details its board surrounding architecture as well as its packaging. However, a fine detailed modeling of board layers layout always exceeds the simulation tool capabilities and requires new modeling methodologies able to define the most significant thermal model. Based on DEvelopment of Libraries of PHysIcal models (DELPHI) methodology, the creation of a compact thermal model, compliant to a set of boundary conditions was investigated for a local board area. The thermal behavior prediction, found to be within ± 5% of error, demonstrates the feasibility of extending the boundary condition independence principle to board modeling in order to achieve a more efficient and accurate board cooling optimization.

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Copyright © 2011 by American Society of Mechanical Engineers
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Figures

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Figure 4

Two Pyramid Stacked Chips in MLF48 package

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Figure 5

Via in pad thermal enhancement for MLF48 cooling

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Figure 6

Design of HDI 3 + 6 + 3 structures

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Figure 7

Cross-section of a typical partially filled and fully filled micro-via

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Figure 8

Improvement of HDI layers heat paths

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Figure 9

Architecture using 16 micro-vias and 25 buried vias

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Figure 10

Domain of board CTM model on an architecture using 25 filled micro-vias and buried vias

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Figure 1

Process flow for determining the most compliant DELPHI type thermal network

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Figure 2

ΔTN = J,BC results for the 49 boundary condition cases

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Figure 3

Standardized board dedicated to IC thermal performances comparison

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