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Research Papers

From Chip to Cooling Tower Data Center Modeling: Influence of Chip Temperature Control Philosophy

[+] Author and Article Information
Ed J. Walsh

 Stokes Institute, University of Limerick, Limerick, Irelandedmond.walsh@ul.ie

Thomas J. Breen

 Stokes Institute, University of Limerick, Limerick, Ireland

Jeff Punch

 CTVR, Stokes Institute, University of Limerick, Limerick, Ireland

Amip J. Shah, Cullen E. Bash

 Hewlett-Packard Laboratories, Palo Alto, CA 94304

J. Electron. Packag 133(3), 031008 (Sep 21, 2011) (6 pages) doi:10.1115/1.4004657 History: Received April 07, 2011; Revised May 09, 2011; Published September 21, 2011; Online September 21, 2011

The chiller cooled data center environment consists of many interlinked elements that are usually treated as individual components. This chain of components and their influences on each other must be considered in determining the benefits of any data center design and operational strategies seeking to improve efficiency, such as temperature controlled fan algorithms. Using the models previously developed by the authors, this paper extends the analysis to include the electronics within the rack through considering the processor heat sink temperature. This has allowed determination of the influence of various cooling strategies on the data center coefficient of performance. The strategy of increasing inlet aisle temperature is examined in some detail and found not to be a robust methodology for improving the overall energy performance of the data center, while tight temperature controls at the chip level consistently provide better performance, yielding more computing per watt of cooling power. These findings are of strong practical relevance for the design of fan control algorithms at the rack level and general operational strategies in data centers. Finally, the impact of heat sink thermal resistance is considered, and the potential data center efficiency gains from improved heat sink designs are discussed.

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Copyright © 2011 by American Society of Mechanical Engineers
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Figures

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Figure 1

Elements within the data center

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Figure 2

Intersection of asymptotes method as proposed by Ref. [12] and employed by Ref. [13]

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Figure 3

Total cooling power required for a range of rack inlet temperatures and the contribution of the room, chiller, and cooling tower for case 1

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Figure 4

Total cooling power required for a range of rack inlet temperatures and the contribution of the room, chiller, and cooling tower for case 2

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Figure 5

COPGrand for variation of rack inlet temperature for cases 1 and 2

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Figure 6

COPGrand for different chip temperature control algorithms

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Figure 7

COPGrand for different fixed chip to heat sink temperature differences. The dashed lines represent fixed heat sink to inlet temperature differences in steps of 5 °C between 20 °C and 45°C from lower to higher COPGrand , respectively

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Figure 8

COPGrand for constant heat sink temperature lines for THS between 40 °C and 65 °C from lower to higher COPGrand , respectively, in steps of 5 °C

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