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Research Papers

Thermo-Mechanical Response of Thru-Silicon Vias Under Local Thermal Transients Using Experimentally Validated Finite Element Models

[+] Author and Article Information
Jamil A. Wakil

Advisory Engineer  IBM Corporation, 11400 Burnet Rd., Austin, TX 78758jwakil@us.ibm.com

Patrick W. Dehaven

Senior Engineer  IBM Corporation, 2070 Rt. 52, Hopewell Junction, NY 12533dehaven@us.ibm.com

Nancy R. Klymko

Senior Technical Staff Member  IBM Corporation, 2070 Rt. 52, Hopewell Junction, NY 12533klymko@us.ibm.com

Shaochen Chen

 University of California San Diego, 9500 Gilman Drive #0448, La Jolla, CA 92093shc064@ucsd.edu

J. Electron. Packag 133(3), 031001 (Sep 14, 2011) (8 pages) doi:10.1115/1.4004656 History: Received March 31, 2010; Revised June 06, 2011; Published September 14, 2011; Online September 14, 2011

Significant research has focused on the reliability of through-silicon-vias (TSVs) under conventional uniform thermal loading conditions such as accelerated thermal cycling (0–100 °C) or deep thermal cycling (−40–125 °C). This study analyzes the thermomechanical behavior of TSVs in 3D packages undergoing rapid local temperature fluctuations, as would be experienced in actual operation. A global/local finite element model is used to analyze the TSV behavior at various distances from the thermal fluctuation site. Transient thermal measurements, warpage and in-plane deformation measurements, as well as micro-Raman spectroscopy measurements are used to validate the model. The results reveal that the short term local temperature transients have minimal impact on the TSV stress state regardless of TSV location, implying that global package- induced stresses dominate.

Copyright © 2011 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Package level and TSV (local) level validation ANSYS models

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Figure 2

Mesh sensitivity analysis for the global package model. Tjmax and laminate warpage as a function of number of elements (left and bottom axis) and Tjmax after 1 s power delta as a function of time step (right and upper axis)

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Figure 3

Schematic showing the module components and lateral dimensions

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Figure 18

Equivalent strain ratio as a function of time for the temperature profile of Fig. 1. (a) shows total time, (b) shows an expanded x-axis near 1s when the power spike occurs.

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Figure 17

Normal z strain ratio (parallel to TSV axis) as a function of time for the temperature profile of Fig. 1. (a) shows total time, (b) shows an expanded time scale near 1 s when the power spike occurs.

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Figure 16

Temperature profile resulting from hotspot power spike at 1 sec, used for TSV mechanical analysis, showing the first 3 s only.

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Figure 15

Model (lines) and measurement (dots) comparison of μRaman shift surrounding two leftmost visible TSV bars. The TSV bars are superimposed on the graph, including the 1 μm of oxide on each side. Measurement uncertainty is estimated to be ±0.2 cm−1 .

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Figure 14

Micro Raman measurement near TSV at top edge of interposer

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Figure 13

High mag picture showing a W TSV bar grouping and locations of μRaman measurements

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Figure 12

Package cross section showing used for μRaman measurements

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Figure 11

Micro Raman measurement system

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Figure 10

Measured spectrum for unstrained Si

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Figure 9

X (along length of cross section) and Y (vertical) field deformations for 150 °C → 25 °C for the 9 × 13 on 11 × 16 mm stack package. Uncertainty of in-plane deformation measurements is estimated to be ±2 μm.

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Figure 8

Lidless chip (a) and laminate backside (b) warpages as function of temperature, measured and modeled, for bare die modules without card. Uncertainty of warpage measurements is estimated to be ± 5 μm.

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Figure 7

Camera setup and measurement volume for 3D DIC measurement

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Figure 6

Model/Experiment comparison for stack package with 9 × 13 mm die on 11 × 16 mm, showing die center, card, and die corner temperatures. Uncertainty of temperature measurements is less than ±1 °C.

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Figure 5

Testing on a cold plate

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Figure 4

Cross section of the 3D stack used for global model validation

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