0
Research Papers

Low Temperature Solid State Gold Bonding of Si Chips to Alumina Substrates

[+] Author and Article Information
Chu-Hsuan Sha1

Electrical Engineering and Computer Science, Materials and Manufacturing Technology,  University of California, Irvine, Irvine, CA 92697-2660

Chin C. Lee

Electrical Engineering and Computer Science, Materials and Manufacturing Technology,  University of California, Irvine, Irvine, CA 92697-2660

1

Corresponding author.

J. Electron. Packag 133(2), 021003 (Jun 22, 2011) (5 pages) doi:10.1115/1.4003868 History: Received October 22, 2010; Revised February 26, 2011; Published June 22, 2011; Online June 22, 2011

Pure gold (Au) is used as a bonding medium to bond silicon (Si) chips to alumina substrates. The bonding process is performed at 260 °C with only 150 psi (1.0 MPa) static pressure applied. This is a solid-state bonding without any molten phase involved. The Au layer plated on alumina is ductile enough to deform for its surface to mate with the thin Au layer coated on Si. Au atoms on both sides of the bond line are brought within atomic distance and bonding is achieved. The ductile Au joint also accommodates the significant mismatch in coefficient of thermal expansion (CTE) between Si and alumina. Scanning electron microscope (SEM) evaluations show that nearly perfect joints are achieved and no voids are observed. Five samples are shear tested. They all pass the MIL-STD-883G standard. This bonding technique can be applied to bonding any two objects that can be coated with smooth Au layers. The 260 °C bonding temperature is compatible with typical reflow temperature of Sn3.5Ag solders used in electronic industries.

FIGURES IN THIS ARTICLE
<>
Copyright © 2011 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Figure 1

Initial bonding design with 25 μm Au plated on upper alumina (not to scale)

Grahic Jump Location
Figure 2

Bonding design of 5 mm × 5 mm Si chip to 8.9 mm × 8.9 mm alumina substrate plated with 25 μm Au (not to scale)

Grahic Jump Location
Figure 3

Cross-section SEM images of poorly bonded sample: (a) low magnification and (b) high magnification. The bonding structure was shown in Fig 1. and the bonding process was performed at 260 °with 1000 psi pressure. Only small Au islands were bonded.

Grahic Jump Location
Figure 4

SEM images showing the microstructure of Au electroplated on alumina/TiW/Au at current density of 6 mA/cm2 : (a) low magnification and (b) high magnification. The average grain size is 20 μm.

Grahic Jump Location
Figure 5

SEM images of the microstructure of 2.54 μm Au layer on alumina/TiW prior to electroplating: (a) low magnification and (b) high magnification. The grains are in submicron range.

Grahic Jump Location
Figure 6

SEM images of Au layer electroplated on alumina/TiW/Au using a plating solution with a brighter at current density of 3 mA/cm2 : (a) low magnification and (b) high magnification. The grain size is 20–40 nm.

Grahic Jump Location
Figure 7

SEM images showing the microstructure of Au layer deposited on Si/Cr by E-beam evaporation: (a) low magnification and (b) high magnification. The grain size is 20–40 nm.

Grahic Jump Location
Figure 8

Cross-section SEM images of a sample bonded with 60 psi pressure at 260 °C: (a) low magnification and (b) high magnification. A thin gap exists along the bonding line.

Grahic Jump Location
Figure 9

Cross-section SEM images of a perfect sample bonded at 260 °C with 150 psi pressure: (a) Si/Au/alumina bonded structure, (b) Si/Au portion where 100 nm Au on Si is bonded to 25 μm Au on alumina, the 30 nm Cr between Si and Au does not show up, and (c) Au/alumina portion.

Grahic Jump Location
Figure 10

Force–displacement curves of five samples during shear test. The fracture force of each sample is indicated. The fracture modes are presented in Table 1.

Grahic Jump Location
Figure 11

Sample C after the shear test. The tool wedge broke off 25% of the chip at a force of 34.5 kg. Majority of the chip is still well bonded to the alumina substrate.

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In