Technical Briefs

Improved Packaging Design for Maximizing the Thermal Performance of Multifinger Collector-Up HBTs

[+] Author and Article Information
Hsien-Cheng Tseng1

Department of Electronic Engineering and Nanotechnology, R&D Center, Kun Shan University, Tainan, Taiwan 71003, R.O.C.hctseng3@ceg.com.tw


Corresponding author.

J. Electron. Packag 133(1), 014501 (Mar 09, 2011) (4 pages) doi:10.1115/1.4003515 History: Received May 29, 2010; Revised December 03, 2010; Published March 09, 2011; Online March 09, 2011

Advanced collector-up (C-up) heterojunction bipolar transistors (HBTs) with the thermal-via configuration (TVC) have been analyzed using a genetic algorithm (GA). Novel packaging structures are presented and evaluated in detail. With careful optimization, the thermal performance can be maximized by improving the thermal resistance over 40%, and the conventional TVC can be further reduced by 35%. The proposed approach is demonstrated on the multifinger InGaP/GaAs C-up HBT, which is attractive as the active component in power amplifiers. A comparison of measured, finite-element-calculated, and GA-extracted results has been made. Consequently, it is shown that the remarkable thermal management can be achieved with a miniature heat-dissipation design, and the thermally stable InGaP/GaAs C-up HBT should be feasible for implementation in intelligent wireless communication systems.

Copyright © 2011 by American Society of Mechanical Engineers
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Grahic Jump Location
Figure 1

The circuit layout of a current-mode logic gate using E-up (upper) and C-up (lower) HBTs (6)

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Figure 2

Schematic of the four-finger InGaP/GaAs C-up HBT with a thermal-via configuration

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Figure 3

Flowchart of the GA optimization approach

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Figure 4

Extraction results of the thermal resistance (symbols: measured data)

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Figure 5

Illustration of the GA optimization with and without the weight function



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