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Research Papers

Translation Solder Self-Alignment Mechanics Modeling for a Flip Chip in the Presence of a Viscous Fluid

[+] Author and Article Information
Brett Fennell, Sangil Lee, Daniel F. Baldwin

The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405

J. Electron. Packag 132(4), 041013 (Dec 08, 2010) (6 pages) doi:10.1115/1.4002825 History: Received November 29, 2009; Revised September 25, 2010; Published December 08, 2010; Online December 08, 2010

Conventional flip chip on board processing involves four major steps: flux application, solder reflow, underfill flow, and underfill cure. The latter two steps are particularly time consuming. To address this issue, a new flip chip process has been developed in which underfill is dispensed prior to chip placement or directly on the wafer and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacturing. However, the presence of the underfill can affect the flip chips’ capacity for self-alignment. Self-alignment occurs in controlled collapse bonding when the solder interconnects become liquidus and, driven by surface tension, pull the chip into registration with the substrate. To study flip chip self-alignment in the presence of underfill, the viscous forces acting on the chip during realignment are modeled after Couette flow and the overall system is modeled as a spring-mass-damper. This paper details the modeling process and includes parametric studies to predict those conditions that are more conducive to alignment, as well as those which are not.

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Copyright © 2010 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Magnified view of chip alignment during direct chip attachment (DCA) and next generation assembly

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Figure 2

Coordinate framework for next generation assembly process modeling

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Figure 3

Restoration force versus misalignment and best fit linear approximation

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Figure 4

Magnified view of next generation test vehicle assembly

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Figure 5

Magnified view of partial free body diagram (FBD) of chip during realignment

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Figure 6

Dampening forces for translation

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Figure 7

Oblique view of die and underfill force distribution

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Figure 8

X-Y plane of die in translational realignment mode

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Figure 9

Effect of offset distance on realignment time using FA10 (4×4)

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Figure 10

Effect of viscosity on realignment time using FA10 (4×4)

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Figure 11

Effect of surface tension on realignment time using FA10 (4×4)

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Figure 12

Effect of interconnect density on realignment time

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