Design Innovation

Silver Flip-Chip Technology by Solid-State Bonding

[+] Author and Article Information
Pin J. Wang1

Electrical Engineering and Computer Science, Materials and Manufacturing Technology, University of California, Irvine, CA 92697-2660pin.wang@intel.com

Chin C. Lee

Electrical Engineering and Computer Science, Materials and Manufacturing Technology, University of California, Irvine, CA 92697-2660


Corresponding author. Present address: Intel Corporation, Chandler.

J. Electron. Packag 132(3), 035001 (Sep 30, 2010) (6 pages) doi:10.1115/1.4002297 History: Received August 31, 2009; Revised May 01, 2010; Published September 30, 2010; Online September 30, 2010

Silver flip-chip joints between silicon (Si) chips and copper (Cu) substrates were fabricated using a solid-state bonding process without any solder and without flux. The bonding process was performed at 250°C, compatible with typical reflow temperature for lead-free solders. During the bonding process, there was no molten phase involved. The Ag joints fabricated consisted of only pure Ag without any intermetallic compound (IMC). Thus, reliability issues associated with IMCs and IMC growth do not exist anymore. Silver has the highest electrical conductivity and highest thermal conductivity among all metals. It is also quite ductile and able to deform to release stresses caused by thermal expansion mismatch. Flip-chip joints of high aspect ratio can be accomplished because the joints stay in a solid state during the bonding process. It looks like that silver is the ultimate joining material for flip-chip as well as through-Si-via interconnect technologies. In this study, the solid-state bonding process was first developed using a pure Ag foil to bond a Si chip to a Cu substrate in one step. The bonding strength on two interfaces, Si/Ag and Ag/Cu, passes the MIL-STD-883G Method 2019.7. To demonstrate Ag flip-chip interconnects, Si chips were electroplated with Ag bumps, followed by the solid-state bonding process on Cu substrates. The flip-chip bumps are well bonded to the Cu substrate. It would take some time for this new technology to be probably accepted and utilized in production. On the other hand, the preliminary results in this study show that Ag flip-chip joints can indeed be fabricated at 250°C.

Copyright © 2010 by American Society of Mechanical Engineers
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Figure 3

Solid-state bonding process between Ag bumps and the Cu substrate: (a) before bonding and (b) after bonding where Ag bumps deformed to accommodate the CTE mismatch between Si and Cu

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Figure 4

Low magnification cross section SEM images of sample A. Cracking in Si chip was caused by epoxy molding and sample dicing operations: (a) and (b) show the different cross section portions of sample A.

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Figure 5

High magnification cross section SEM image of sample A: (a) the Si/Ag interface and (b) the Ag/Cu interface

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Figure 6

Optical picture of sample F showing the breakage inside the Si chip after the shear test

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Figure 7

Optical picture of sample B after shear test on the Ag foil. The sheared Ag foil curled upwards and stayed on the sample

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Figure 8

Force-displacement curves of Ag foils on samples B and C during the shear test. The Ag foil exhibited remarkable yielding behavior.

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Figure 14

High magnification SEM images of Ag joint 6 in Fig. 1: (a) Ag joint 6 and (b) Ag/Cu interface

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Figure 13

High magnification SEM images of Ag joint 2 in Fig. 1: (a) Ag joint 2, (b) Si/Ag interface, where the thin Cr/Au layers between Si and Ag cannot be seen, and (c) Ag/Cu interface

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Figure 12

SEM image on a cross section of sample G that exhibits 10 Ag joints in one row of the 10×10 array: (a) Ag joints 1–5, (b) Ag joints 6–10

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Figure 11

SEM images of Ag bumps after photoresist stripping viewed at 45 deg angle: (a) low magnification (×100) and (b) high magnification (×600)

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Figure 10

The surface profile of a typical Ag bump showing a profile variation of ±2 μm with an average height of 45 μm

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Figure 9

SEM images of photoresist pattern viewed at 45 deg angle: (a) low magnification (×100) and (b) high magnification (×600)

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Figure 2

Fabrication process of Ag bumps on the Si wafer by electroplating: (a) photoresist coating and UV light exposure through a photomask, (b) photoresist with cavities after development, (c) Ag electroplated in cavities, and (d) Ag bumps on the Si wafer after photoresist stripping

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Figure 1

Experiment structure for developing solid-state bonding of Si chips on Ag foils on Cu substrates




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