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Research Papers

Multi-Objective Optimization to Improve Both Thermal and Device Performance of a Nonuniformly Powered Micro-Architecture

[+] Author and Article Information
Saket Karajgikar

 University of Texas at Arlington, Arlington, TX 76019saket@mech.uta.edu

Dereje Agonafer

 University of Texas at Arlington, Arlington, TX 76019agonafer@uta.edu

Kanad Ghose

 SUNY Binghamton, Binghamton, NY 13902ghose@cs.binghamton.edu

Bahgat Sammakia

 SUNY Binghamton, Binghamton, NY 13902bahgat@binghamton.edu

Cristina Amon

 University of Toronto, Toronto, ON, M5S3G8, Canadaamon@mie.utoronto.ca

Gamal Refai-Ahmed

 Advanced Micro Devices, Inc., Markham, ON, L3t 7X6, Canadagamal.refai-ahmed@amd.com

J. Electron. Packag 132(2), 021008 (Jun 25, 2010) (8 pages) doi:10.1115/1.4001852 History: Received October 28, 2009; Revised May 03, 2010; Published June 25, 2010; Online June 25, 2010

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, and memory controller has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly nonuniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can affect performance by a factor as much as 30%. In this paper, a multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. The analysis was performed for 90 nm Pentium IV Northwood architecture operating at 3 GHz clock speed. Each functional unit on the die has a specific role, so functional units with similar roles were grouped together. Thus, the actual Pentium IV die was divided into four groups (front end, execution cores, bus and L2, and out-of-order engine). Repositioning constraints were determined using circuit delay models of major functional units in a micro-architectural simulator. Thus, depending on the scenario, relocating functional units can result in virtually no performance loss (less than 2% is assumed to be minimal and is reported as 0%) to as much as 30% performance loss. From the results, the minimum and the maximum temperatures were 56.6°C and 62.2°C. This ΔT corresponds to thermal design power of 60.2 W. For microprocessors with higher thermal design power (115 W) and operating at higher clock speed, higher ΔT can be realized. Based on this paper’s analysis, the optimized scenario resulted in a junction temperature of 56.6°C at the cost of a 14% performance loss.

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Copyright © 2010 by American Society of Mechanical Engineers
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Figures

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Figure 2

Model of a flip-chip package considered for analysis

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Figure 3

Pentium IV floor plan. (a) Pictorial view (17). (b) Functional block redistribution (14).

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Figure 4

Grouping of different functional blocks for the baseline case of Pentium IV architecture

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Figure 5

Functional groups of Pentium IV architecture: (a) group 1, (b) group 2, (c) group 3, and (d) group 4

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Figure 6

Temperature contours for the baseline scenario (nonuniform power)

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Figure 7

Temperature contours for uniform power distribution

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Figure 8

Temperature contours and the corresponding functional unit location for one of the scenarios depicting junction temperature less than 57°C. (a) Temperature contour. (b) Location of functional units.

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Figure 9

Original and new (corresponding to Fig. 8) locations of functional units in group 2: (a) original location and (b) new/optimized location

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Figure 10

Temperature contour and location of functional units for the optimized scenario: (a) temperature contour and (b) location of functional units

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Figure 1

Hot spots as an effect of nonuniform power on two Intel processors. (a) Pentium III processor and (b) Itanium processor (4)

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