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Research Papers

Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package

[+] Author and Article Information
Hu Guojun

 STMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singaporeguojun.hu@st.com

Andrew A. O. Tay

Department of Mechanical Engineering, Nano/Microsystems Integration Laboratory,National University of Singapore

Luan Jing-En, Ma Yiyi

 STMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore

J. Electron. Packag 132(1), 011006 (Mar 19, 2010) (7 pages) doi:10.1115/1.4001145 History: Received February 14, 2009; Revised January 10, 2010; Published March 19, 2010; Online March 19, 2010

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.

Copyright © 2010 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

2D eight-node singular element

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Figure 2

A crack along a bimaterial interface

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Figure 3

Interface crack subjected to uniform tension and shear

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Figure 4

Variation in energy release rates under mixed load

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Figure 5

Variation in phase angle under mixed load

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Figure 6

Chemical cure shrinkage and thermal shrinkage during transfer molding

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Figure 7

Storage modulus of underfill based on the dynamic mechanical analyzer

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Figure 8

Schematic of the flip chip BGA

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Figure 9

Die/EMC interface delamination—FEA

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Figure 10

Comparison of energy release rates and Von Mises stress at room temperature

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Comparison of energy release rates and Von Mises stress at reflow temperature

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Figure 12

Comparison of phase angles at reflow temperature

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Phase angle dependent interface fracture toughness (25)

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Figure 14

Comparison of failure rate of the flip chip BGA package due to interface delamination

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Figure 15

CSAM results of interface delamination between silicon die and epoxy molding compound: (a) flip chip BGA using underfill 1, (b) flip chip BGA using underfill 2, and (c) flip chip BGA using underfill 3

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Figure 16

Example FEA meshed for three different fillet configurations (50 μm, 150 μm, and 250 μm): (a) FEA mesh for the 50 μm fillet configuration, (b) FEA mesh for the 150 μm fillet configuration, and (c) FEA mesh for the 250 μm fillet configuration

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Effect of underfill fillet height on energy release rates

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Figure 18

Effect of underfill fillet height on the interface phase angles

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Figure 19

Effect of die thickness on energy release rates

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Figure 20

Effect of die thickness on the interface phase angles

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