Research Papers

Reliability Modeling of Lead-Free Solder Joints in Wafer-Level Chip Scale Packages

[+] Author and Article Information
Jie-Hua Zhao

 Texas Instruments Incorporated, 13536 North Central Expressway, MS940, Dallas TX 75243jhzhao@ti.com

Vikas Gupta, Alok Lohia, Darvin Edwards

 Texas Instruments Incorporated, 13536 North Central Expressway, MS940, Dallas TX 75243

J. Electron. Packag 132(1), 011005 (Mar 04, 2010) (6 pages) doi:10.1115/1.4000754 History: Received December 17, 2008; Revised September 30, 2009; Published March 04, 2010; Online March 04, 2010

Board-level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSPs) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep, and time-hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared with experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.

Copyright © 2010 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.



Grahic Jump Location
Figure 2

Reliability test data for −40°C to 125°C temperature cycles, the cycle time is 30 min; five different WLCSP packages were tested. The solder ball pitch is 0.5 mm for each package, except for the 25 pin package, which has a ball pitch of 0.4 mm.

Grahic Jump Location
Figure 3

A typical cross-sectional micrograph of a failed solder joint taken under the scanning electron microscope. The fatigue crack path is in the solder ball and along a thin layer of solder connecting to the die.

Grahic Jump Location
Figure 4

The FEM mesh of the 30 pin WCSP. One-quarter of the package and board was modeled. Proper symmetry boundary conditions were imposed to ensure the full structure was represented correctly.

Grahic Jump Location
Figure 5

The contour plot of inelastic strain energy density of the solder balls for the 30 pin WCSP at the end of the first loading step (at −40°C). The critical solder joint is at the outmost corner, which is shown in the upper center in the figure. The units are in MPa.

Grahic Jump Location
Figure 6

Linear regressions of the logarithm of characteristic life (log10(N)) versus the logarithm of increment of volume-averaged inelastic strain energy density per cycle across the cracking path (log10(ΔW/MPa)). Three different constitutive models were examined. The correlation factor is better than 0.95 for all three cases.

Grahic Jump Location
Figure 1

Package drawings of five wafer-level chip scale packages. The pin counts are 64, 30, 25, 5, and 4. The solder ball pitches are 0.5 mm except for the 25 pin package, which has 0.4 mm ball pitch.




Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In