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Technical Briefs

Novel Design of Thermal-Via Configurations for Collector-Up HBTs

[+] Author and Article Information
Pei-Hsuan Lee, Jung-Hua Chou

Department of Engineering Science, National Cheng Kung University, Tainan 70101, Taiwan, R.O.C.

Hsien-Cheng Tseng1

Department of Electronic Engineering and Nanotechnology, R&D Center, Kun Shan University, Tainan 71003, Taiwan, R.O.C.j41528@mail.ksu.edu.tw

1

Corresponding author.

J. Electron. Packag 131(4), 044501 (Oct 21, 2009) (3 pages) doi:10.1115/1.4000282 History: Received August 21, 2008; Revised September 17, 2009; Published October 21, 2009

We devise a finite-element model to analyze the thermal performance of collector-up (C-up) heterojunction bipolar transistors (HBTs) with a thermal-via configuration. A demonstration on the GaInP/GaAs C-up HBT is presented in this Brief, and the novelty of this work is that both 2D and 3D temperature-distribution analyses are performed. The 2D results indicate that the original thermal-via configuration can be reduced by 29%. Furthermore, the results show that the maximum temperature within the collector calculated from 3D analysis is lower than that from the 2D analysis. Based on the 3D analysis, it is revealed that the reported configuration can be reduced by 32%. Therefore, the C-up HBT with a compact thermal-via should be helpful for miniaturization of heat-dissipation packaging configurations within HBT-based high-power amplifiers.

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Copyright © 2009 by American Society of Mechanical Engineers
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Figures

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Figure 1

Cross-sectional view of the GaInP/GaAs C-up HBT with the thermal-via configuration

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Figure 2

The grid independent test

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Figure 3

Temperature distribution of the GaInP/GaAs C-up HBT

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Figure 4

The maximum temperature in the GaInP/GaAs C-up HBT by adjusting the thicknesses of the PHS layer and the GaAs substrate in 2D analysis

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Figure 5

The maximum temperature in the GaInP/GaAs C-up HBT

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