0
Research Papers

Effect of Warpage of Flip Chip Packages Due to the Underfill Encapsulating Process on Interconnect Reliability

[+] Author and Article Information
Satoru Katsurayama

Electronic Device Material Research Laboratories II, Sumitomo Bakelite Co Ltd., Kiyohara Industrial Park 20-7, Utsunomiya, Tochigi 321-3231, Japankaturas@sumibe.co.jp

Hironori Tohmyoh

Department of Nanomechanics, Tohoku University, Aoba 6-6-01, Aramaki, Aoba-ku, Sendai 980-8579, Japan

J. Electron. Packag 131(3), 031005 (Jun 23, 2009) (5 pages) doi:10.1115/1.3144153 History: Received September 18, 2008; Revised April 16, 2009; Published June 23, 2009

In flip chip packages, it is common practice for interconnects to be encapsulated with a liquid underfill material. This paper describes the effects of different underfill processes, i.e., the conventional capillary-flow underfill and two no-flow underfill processes, on flip chip packaging. The warpage of the package was examined, and the value of this during three different underfill encapsulating processes was measured. In addition, the interconnect reliability of the bump bonds after thermal-cycling was evaluated using a test circuit. The warpage of the package before curing varied depending on the assembly process, but that after curing was almost the same for all the processes studied. It was found that the interconnect reliability is closely related to the differences in the warpage arising from the assembly process, and that the smaller change in warpage introduced by the curing process gave a higher interconnect reliability for the bump bonds. Based on these findings, lower curing temperatures are considered to be more effective for improving the mountability of the package and the interconnect reliability.

FIGURES IN THIS ARTICLE
<>
Copyright © 2009 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Figure 1

Details of the test sample: (a) printed circuit board and (b) I/O arrangement at the back of the silicon chip

Grahic Jump Location
Figure 2

Typical encapsulation processes for F/C package: (a) CUF process and (b) NUF process

Grahic Jump Location
Figure 3

Temperature profiles for the CUF and NUF processes (a) and the temperature and pressure histories in the NUF-TC process is also shown in (b)

Grahic Jump Location
Figure 4

Displacement profiles at the surface of the package substrate after chip assembly for the (a) CUF, (b) NUF, and (c) NUF-TC processes, respectively. Profiles after curing for the (d) CUF, (e) NUF, and (f) NUF-TC processes, respectively.

Grahic Jump Location
Figure 5

Relationship between IR and the number of TCs for each process

Grahic Jump Location
Figure 6

An example of a cross-sectional view of bump failure, which was observed after 500 TCs of a bump built by the NUF-TC process

Grahic Jump Location
Figure 7

Relationship between IR after 500 TCs and Δ

Grahic Jump Location
Figure 8

Effect of curing temperature on (a) δ and (b) IR

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In