Research Papers

Thermal Solution Maps: A Strategy for Thermal Design of Three-Dimensional Packages

[+] Author and Article Information
M. Rayasam, G. Subbarayan

School of Mechanical Engineering, Purdue University, West Lafayette, IN 47907-2088

S. Chaparala, D. Farnam, B. G. Sammakia

Small Scale Systems Integration and Packaging Center, SUNY at Binghamton, Binghamton, NY 13902

J. Electron. Packag 131(1), 011015 (Feb 25, 2009) (9 pages) doi:10.1115/1.3077131 History: Received May 07, 2008; Revised May 30, 2008; Published February 25, 2009

Three-dimensional (3D) packages are of considerable interest at the present time as a means for heterogeneous high-performance integration of disparate digital, analog, optical, and MEMS technologies. However, their design is challenged by several issues, including the appropriate choice of thermal solution to be used in the 3D stack. Suboptimal placement of heat sources/sinks leads to hot spots, which are detrimental to package reliability. The broad goals of this study are to determine the appropriate cost and reliability-constrained heat-sinking solutions through an optimal placement of spatially distributed energy transporting elements. The heat-sinking solutions considered in this study include microchannels, and thermal vias. We conduct a microchannel analysis to develop a reduced model of the heat and mass transfer characteristics of the microchannel. We also develop optimization techniques and tools for thermal solution design of three-dimensional packages. We use a nonuniform “real-life” microprocessor power map for the illustration of the procedure. We subsequently obtain the optimal size and location of the thermal vias and microchannels in a 3D stack by minimizing a proposed multi-objective criteria. Finally, we develop and illustrate the notion of design maps that would guide the designers in the selection of appropriate thermal solution technologies for 3D packages.

Copyright © 2009 by American Society of Mechanical Engineers
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Figure 1

(a) 3D IC (courtesy of IBM) and (b) 3D Package (courtesy of AMKOR)

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Figure 2

Schematic of microchannels and thermal vias embedded in the package (top) and power map of a typical microprocessor (bottom, courtesy of IBM)

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Figure 3

Possible thermal design solutions for 3D packages

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Figure 4

Schematic of the silicon chip with embedded microchannels (left) and schematic of the microchannel (right)

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Figure 5

Mesh sensitivity study (top) and velocity profile along the channel (bottom)

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Figure 6

Variation in h along the channel for various flow velocities (top) and Nusselt number versus nondimensional parameter x∗ (bottom)

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Figure 7

(a)–(d) Various microchannel configurations

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Figure 8

Temperature distributions corresponding to various microchannel configurations (a)–(d)

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Figure 9

(a) Schematic of a package with a microchannel (left) and (b) thermal via (right)

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Figure 10

Design map of the package with a microchannel

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Figure 11

Design map of the package with a thermal via

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Figure 12

Design maps of microchannel and thermal via

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Figure 13

(a) Schematic of a three-dimensional package, with constant material density along the height (left) and (b) optimal distribution of high density material in its cross section (darker areas on the right side of the picture indicate high conductivity regions)




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