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Research Papers

Correlating Drop Impact Simulations With Drop Impact Testing Using High-Speed Camera Measurements

[+] Author and Article Information
J. J. M. Zaal1

 Delft University of Technology, Delft 2628CD, The Netherlandsj.j.m.zaal@tudelft.nl

W. D. van Driel

 NXP Semiconductors, Nijmegen 6534 AE, The Netherlands; Delft University of Technology, Delft 2628CD, The Netherlands

F. J. H. G. Kessels

 NXP Semiconductors, Nijmegen 6534 AE, The Netherlands

G. Q. Zhang

 NXP Semiconductors, Nijmegen, The Netherlands; Delft University of Technology, Delft 2628CD, The Netherlands

1

Corresponding author.

J. Electron. Packag 131(1), 011007 (Feb 12, 2009) (9 pages) doi:10.1115/1.3068311 History: Received December 27, 2007; Revised August 07, 2008; Published February 12, 2009

The increased use of mobile appliances such as mobile phones and navigation systems in today’s society has resulted in an increase in reliability issues related to drop performance. Mobile appliances are dropped several times during their lifespan and the product is required to survive common drop accidents. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. This test has been standardized by international councils such as Joint Electron Device Engineering Council and is widely adopted throughout the industry. In this research the solder loading is investigated by combining high-speed camera measurements of several drop impact tests with verified finite element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on interconnect layout, drop conditions, and product specifications prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: machine level (rebounds with and without a catcher) and product level (with different levels of energy and different pulse times). Parametric (dynamic and quasistatic) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g., by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.

Copyright © 2009 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

The JEDEC specified drop impact setup (7)

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Figure 2

Drop impact tester (DIT) experimental setup

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Figure 3

PCB with products and solder

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Figure 4

(a) Solder ball layout; (b) mesh around a product

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Figure 5

Typical frames in a drop impact test with (a) the impact mass with reference bar entering the field of view, (b) the impact mass at its lowest point, and (c) the drop mass moving back upwards

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Figure 6

Impact mass position above the strike surface

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Figure 7

Typical frames in a drop impact test with (a) descent of the mass toward the strike pad, (b) entrance of the PCB into the field of view, (c) highlighted PCB against black background, (d) initial impact, (e) rebound, mass moving up again, and (f) mass and PCB moving out of the field of view

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Figure 8

Typical result from the image-processing module

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Figure 9

PCB center deflection

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Figure 10

Supplier A PCB amplitudes after a 1500 g, 1 ms impact (measurement numbers do not correspond to Table 3)

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Figure 11

Supplier B PCB amplitudes after a 1500 g, 1 ms impact

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Figure 12

Three loading levels

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Figure 13

Comparison of the simulation amplitudes with the measured amplitudes

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Figure 14

Comparison of the simulation response with the measured response

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Figure 15

Normalized solder ball strains

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Figure 16

Normalized solder ball strains on the middle product

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