Research Papers

Development of Analytical Model to a Temperature Distribution of a First Level Package With a Nonuniformly Powered Die

[+] Author and Article Information
Abhijit Kaisare

Department of Mechanical and Aerospace Engineering, Electronics, MEMS and Nano Systems Packaging Center, University of Texas at Arlington, Arlington, TX 76010kaisare@mech.uta.edu

Dereje Agonafer, A. Haji-Sheikh

Department of Mechanical and Aerospace Engineering, Electronics, MEMS and Nano Systems Packaging Center, University of Texas at Arlington, Arlington, TX 76010

Greg Chrysler, Ravi Mahajan

 Intel Corporation, 5000 W. Chandler Blvd., Chandler, AZ 85226

J. Electron. Packag 131(1), 011005 (Feb 12, 2009) (7 pages) doi:10.1115/1.3068303 History: Received November 18, 2007; Revised May 15, 2008; Published February 12, 2009

Microprocessors continue to grow in capabilities, complexity, and performance. Microprocessors typically integrate functional components such as logic and level two cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly nonuniform, and the assumption of a uniform heat flux across the die surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work (Kaisare, 2005, “Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die,” InterPACK 2005, San Francisco, CA, Jul. 17–22) has been done, which includes numerical analysis and thermal based optimization of a typical package consisting of a nonuniformly powered die, heat spreader, thermal interface materials I and II, and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a nonuniformly powered die is carried out for the first time. The analytical model for two-layer bodies developed by Haji-Sheikh (2003, “Steady-State Heat Conduction in Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 46(13), pp. 2363–2379) is extended to this typical package, which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology is applied to solve the equations for various surfaces to calculate the maximum junction temperature for a given multilayer body. Finally validation of the analytical solution is carried out using previously developed numerical model.

Copyright © 2009 by American Society of Mechanical Engineers
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Figure 2

Schematic of a given attachment (11-12)

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Figure 3

Schematic of a two-layer body (10)

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Figure 4

Schematic of the regions being studied

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Figure 5

Step 1: (a) TIM II and IHS and (b) boundary conditions

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Figure 6

Step 2: (a) TIM I and die and (b) boundary conditions

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Figure 7

Values of TI and TII at interfaces from steps 1 and 2

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Figure 8

Flowchart for developing analytical model for nonuniformly powered microprocessor

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Figure 9

Temperature distribution for distribution of uniform heat flux over a die surface

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Figure 10

Validation of junction temperature (Tj) for die for numerical and analytical models for different cases

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Figure 11

Temperature distribution over a given die surface for (a) 4×4 power map and (b) 5×5 power map

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Figure 1

Impact of die power nonuniformity on cooling capability (9)




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