0
Technical Briefs

Flip-Chip Interconnect for Coplanar Strip Lines

[+] Author and Article Information
Young K. Song

Electrical Engineering and Computer Science, University of California, Irvine, CA 92697-2625

Chin C. Lee

Electrical Engineering and Computer Science, University of California, Irvine, CA 92697-2625cclee@uci.edu

J. Electron. Packag 130(4), 044501 (Nov 17, 2008) (4 pages) doi:10.1115/1.2993140 History: Received December 11, 2007; Revised April 09, 2008; Published November 17, 2008

A flip-chip interconnect configuration with coplanar strip (CPS) lines on printed circuit boards (PCBs) is reported for millimeter-wave applications. For CPS lines, the signal and ground electrodes both lie on the top surface of a chip or substrate. The flip-chip configuration was designed and implemented using a test chip on a dielectric board. Geometrical parameter analysis was carried out using full-wave simulation and equivalent circuit model for wideband performance. The chip was connected to the board using solder bumps. For a typical flip-chip assembly, the measured insertion loss is less than 3dB for frequencies of up to 35GHz and the return loss is higher than 15dB for frequencies of up to 29GHz using CPS flip-chip configuration.

FIGURES IN THIS ARTICLE
<>
Copyright © 2008 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Figure 3

(a) Geometrical design parameters of CPS flip-chip interconnect, (b) CPS line on chip side, (c) CPS lines and solder balls on the board. CPS lines have electrode width of 850μm, gap of 60μm, and electrode thickness of 17μm. The thicknesses of the board and chip are 535μm and 385μm, respectively. The board is TMM10 (9) with permittivity of 9.2, loss tangent of 0.0022, and 0.5oz copper cladding. Pitch distance d between solder balls is 790μm. Conductor-overlap length (CO) is 380μm. Dielectric-overlap length (DO) is 100μm.

Grahic Jump Location
Figure 4

Equivalent circuit model of solder bump interconnect

Grahic Jump Location
Figure 5

Optical picture and X-ray image the flip-chip assembly

Grahic Jump Location
Figure 6

Return loss (S11) and insertion loss (S21) of a typical flip-chip assembly.

Grahic Jump Location
Figure 2

A new flip-chip interconnect configuration with coplanar strip (CPS) lines.

Grahic Jump Location
Figure 1

Cross section end views of (a) microstrip line, (b) CPW, (c) CPS line with dielectric backside, and (d) CPS line with metallized backside

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In