De Kock, D. J., Visser, J. A., Nair, R., Nagulapally, M., and Nigen, J., 2005, “Mathematical Optimization of Electronic Enclosures,” "*Proceeding of the ASME InterPACK*", San Francisco, CA.

Scholand, A. J., Fulton, R. E., and Bras, B., 1999, “Investigation of PWB Layout by Genetic Algorithms to Maximize Fatigue Life,” ASME J. Electron. Packag.

[CrossRef], 121 (1), pp. 31–36.

Queipo, N. V., Humphrey, J. A. C., and Ortega, A., 1998, “Multiobjective Optimal Placement of Convectively Cooled Electronic Components on Printed Wiring Boards,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A

[CrossRef], 21 (1), pp. 142–153.

Stoyanov, S., Bailey, C., and Cross, M., 2002, “Optimisation Modelling for Flip-Chip Solder Joint Reliability,” Soldering Surf. Mount Technol.

[CrossRef], 14 (1), pp. 49–58.

Tsai, C.-H., and Kang, S.-M., 2000, “Cell-Level Placement for Improving Substrate Thermal Distribution,” IEEE Trans. Comput.-Aided Des.

[CrossRef], 19 (2), pp. 253–266.

Belady, C. L., and Minichiello, A., 2003, “Effective Thermal Design for Electronic Systems,” Electronics Cooling, 9 (2), pp. 16–21.

Tummala, R., 2001, "*Fundamentals of Microsystems Packaging*", McGraw-Hill, New York.

Lasance, C. J. M., 1995, “The Need for a Change in Thermal Design Philosophy,” Electronics Cooling, 1 (2), pp. 24–26.

Lindell, M., Stoaks, P., Carey, D., and Sandborn, P., 1998, “The Role of Physical Implementation in Virtual Prototyping of Electronic Systems,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A

[CrossRef], 21 , pp. 611–616.

Zhang, G. Q., Bisschop, J., and Maessen, P., 2001, “Virtual Thermo-Mechanical Prototyping of Microelectronics Products—Towards Optimized Designing in Reliability,” Adv. Microelectron., 28 (1),

http://www.imaps.org/adv_micro/2001jan_feb/2.html.

Francois-Saint-Cyr, A., 2005, “Technical Brief: Solve Thermal Issues Earlier in Updated Board Designs,” Electronics Cooling, 11 (1), pp. 36–38.

Sandborn, P. A., and Vertal, M., 1998, “Analyzing Packaging Trade-Offs During System Design,” IEEE Des. Test, 15 (3), pp. 10–19.

Glover, R., 1996, “PCB Leapfrogs Into System-Level Design,” Electronic Design, 44 (7), pp. 83–84.

Fulton, R. E., 1995, “Trends in Electronic Mechanical CAD Integration,” "*Proceedings of the ASME InterPACK*", Maui, HI.

Coulibaly, I., 1998, “METHODIC: A New CAD for Electrothermal Coupling Simulation in Power Converters,” "*Proceedings of the Industrial Electronics Conference*", Aachen, Germany.

Sandborn, P. A., and McFall, G., 1996, “Performing Design for Environment Concurrent With Interdisciplinary Tradeoff Analysis of Electronic Systems,” "*Proceedings of the ISEE-1996*", Dallas, TX.

Pesare, M., Giorgio, A., Passaro, V. M. N., and Perri, A. G., 2000, “Electrothermal Modelling of GaAs MESFETs,” Int. J. Electron., 87 (10), pp. 1163–1170.

Denis, D., Hunter, I. C., and Snowden, C. M., 2005, “Design of Power FETs Based on Coupled Electro-Thermal-Electromagnetic Modeling,” "*Proceedings of the IEEE MTT-S International Microwave Symposium*".

Choksi, G., Immaneni, L., Karunakaran, R., Lin, Y. C., Stys, D., and Wyllie, M., 1995, “Package Design Advisor—Mechanical, Electrical and Thermal Analysis in One CAD Tool,” "*Proceedings of the IEEE Electronic Components and Technology*", Las Vegas, NV.

Farbarik, R., Liu, X., Rossman, M., Parakh, P., Basso, T., and Brown, R., 1997, “CAD Tools for Area-Distributed I/O Pad Packaging,” "*Proceedings of the IEEE MCMC ‘97*", Santa Cruz, CA.

Blood, W., and Lai, A., 1998, “Early Analysis of Chip Scale Package Design Trade-Offs,” "*Proceedings of the IEEE IC/Package Design Integration*", Santa Cruz, CA.

Wu, P., Chen, K., and Tzou, J., 1997, “ViperBGA: A Novel Design Approach to High Performance and High Density BGA’s,” "*Proceedings of the Electronic Manufacturing Technology Symposium*".

Wilde, J., Staiger, W., Thoben, M., Schuch, B., and Kilian, H., 1998, “Integration of Liquid Cooling Thermal and Thermomechanical Design for the Lifetime Prediction of Electrical Power Modules,” "*Proceedings of the SAE International Congress and Exposition*", Detroit, MI.

Cwik, T., Katz, D. S., and Villegas, F., 2001, “Integrated Design and Simulation for Millimeter-Wave Antenna Systems,” "*Proceedings of the IEEE Aerospace Conference*", Big Sky, MT.

Staton, D. A., 2001, “Thermal Computer Aided Design-Advancing the Revolution in Compact Motors,” "*Proceedings of the Electric Machines and Drives Conference*".

Przekwas, A., 1999, “Integrated Multidisciplinary CAD/CAE Environment for Micro-Electro-Mechanical Systems (MEMS),” "*Proceedings of the SPIE International Society Optical Engineering*", Paris, France.

Stout, P., Yang, H. Q., Dionne, P., Leonard, A., Tan, Z., Przekwas, A., and Krishnan, A., 1999, “CFD-ACE+MEMS: A CAD System for Simulation and Modeling of MEMS,” "*Proceedings of the SPIE International Society Optical Engineering*", Paris, France.

Zhou, W. X., Hsiung, C. H., Fulton, R. E., Yin, X. F., Yeh, C. P., and Wyatt, K., 1997, “CAD-Based Analysis Tools for Electronic Packaging Design (A New Modeling Methodology for a Virtual Development Environment),” "*Proceedings of the ASME InterPACK*", Kohala Coast, HI.

Zhou, W. X., 1997, “Modularized and Parametric Modeling Methodology for Concurrent Mechanical Design of Electronic Packaging,” Ph.D. thesis, Georgia Institute of Technology, Atlanta, GA.

Assouad, Y., Etienne, P., and Labaune, G., 1997, “Thermal/EMC Optimization of Airborne Electronic Racks,” "*Proceedings of the International System Packaging Symposium*", San Diego, CA.

Tian, X., and Palusinski, O. A., 2002, “Reliability, Thermal Analysis and Optimization Wirability Design of Multi-Layer PCB Boards,” "*Proceedings of the IEEE Reliability and Maintainability Symposium*", Seattle, WA.

Mottahed, B. D., and Manoochehri, S., 2000, “Optimal Design of Electronic System Utilizing an Integrated Multidisciplinary Process,” IEEE Trans. Adv. Packag.

[CrossRef], 23 , pp. 699–707.

Chen, R., Canales, F., Yang, B., and van Wyk, J. D., 2002, “Volumetric Optimal Design of Passive Integrated Power Electronic Module (IPEM) for Distributed Power System (DPS) Front-End DC/DC Converter,” Proceedings of the Industry Applications Conference, 37th IAS Annual Meeting, Vol. 3 , pp. 1758–1765.

Larouci, C., Ferrieux, J. P., Gerbaud, L., Roudet, J., and Keradec, J. P., 2002, “Volume Optimization of a PFC Flyback Structure Under Electromagnetic Compatibility, Loss and Temperature Constraints,” "*Proceedings of the IEEE Power Electronics Specialists Conference*", Cairns, Australia.

Blaabjerg, F., and Pedersen, J. K., 1997, “Optimized Design of a Complete Three-Phase PWM-VS Inverter,” IEEE Trans. Power Electron.

[CrossRef], 12 (3), pp. 567–577.

Wagner, G. R., 2000, “Optimization of the Arcticooler for Lowest Thermal Resistance in a Minimum Volume,” "*Proceedings of the ITHERM*", Las Vegas, NV.

Loh, C. K., Nelson, D., and Chou, D. J., 2001, “Optimization of the Fan-Heat Sink Systems in Portable Electronics Environment,” "*Proceedings of the SPIE HD International Conference on High-Density Interconnect and Systems Packaging*", Santa Clara, CA.

Zhang, W., Lee, F. C., and Chen, D. Y., 2000, “Integrated EMI/Thermal Design for Switching Power Supplies,” "*Proceedings of the Power Electronics Specialists Conference*".

Rieh, J.-S., Greenberg, D., Liu, Q., Joseph, A. J., Freeman, G., and Ahlgren, D. C., 2005, “Structure Optimization of Trench-Isolated SiGe HBTs for Simultaneous Improvements in Thermal and Electrical Performances,” IEEE Trans. Electron Devices

[CrossRef], 52 (12), pp. 2744–2752.

Li, P., Deng, Y., and Pileggi, L. T., 2005, “Temperature-Dependent Optimization of Cache Leakage Power Dissipation,” "*Proceedings of the International Conference on Computer Design*".

Chen, S.-C., and Culpepper, M. L., 2005, “Design and Optimization of Thermomechanical Actuator Via Contour Shaping,” "*Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems*".

Chen, J. Z., Wu, Y., Gence, C., Boroyevich, D., and Bohn, J. H., 2001, “Integrated Electrical and Thermal Analysis of Integrated Power Electronics Modules Using iSIGHT,” "*Proceedings of the IEEE APEC*", Anaheim, CA.

Stoyanov, S., Bailey, C., Lu, H., and Cross, M., 2001, “Solder Joint Reliability Optimization,” "*Proceedings of the APACK*", Singapore.

Stoyanov, S., Bailey, C., Lu, H., and Cross, M., 2002, “Integrated Computational Mechanics and Optimization for Design of Electronic Components,” "*Optimization in Industry*", I.C.Parmee and P.Hajela, eds., Springer-Verlag, London, pp. 57–70.

Hossain, M. M., Jagarkal, S. G., Agonafer, D., Lulu, M., and Reh, S., 2007, “Design Optimization and Reliability of PWB Level Electronic Package,” ASME J. Electron. Packag.

[CrossRef], 129 (1), pp. 9–18.

Hadim, H., and Suwa, T., 2005, “A Multidisciplinary Design and Optimization Methodology for Ball Grid Array Packages Using Artificial Neural Networks,” ASME J. Electron. Packag.

[CrossRef], 127 (3), pp. 306–313.

Wang, T.-Y., Tsai, J.-L., and Chung-Ping Chen, C., 2004, “Thermal and Power Integrity Based Power/Ground Networks Optimization,” "*Proceedings of the Design, Automation and Test in Europe Conference and Exhibition*".

Nagata, M., Swart, N., Stevens, M., and Nathan, A., 1995, “Thermal Based Micro Flow Sensor Optimization Using Coupled Electrothermal Numerical Simulations,” "*Proceedings of the International Conference on Solid-State Sensors and Actuators, and Eurosensors*", Stockholm, Sweden.

Beratlis, N., and Smith, M. K., 2003, “Optimization of Synthetic Jet Cooling for Microelectronics Applications,” "*Proceedings of the IEEE SEMI-THERM*", San Jose, CA.

Chen, G., Rentzch, M., Wang, F., Boroyevich, D., Ragon, S., Stefanovic, V., and Arpilliere, M., 2003, “Analysis and Design Optimization of Front-End Passive Components for Voltage Source Inverters,” "*Proceedings of the IEEE APEC*", Miami Beach, FL.

Rajan, S. D., and Nagaraj, B., 1995, “Towards Enhancing the Life of Plastic Power Packages Using Design Optimization,” "*Proceedings of the ASME InterPACK*", Maui, HI.

Liu, D.-S., Ni, C.-Y., and Chen, C.-Y., 2003, “Integrated Design Method for Flip Chip CSP With Electrical, Thermal and Thermo-Mechanical Qualifications,” Finite Elem. Anal. Design, 39 (7), pp. 661–677.

Xu, L., Reinikainen, T., Ren, W., Wang, B. P., Han, Z., and Agonafer, D., 2004, “A Simulation-Based Multi-Objective Design Optimization of Electronic Packages Under Thermal Cycling and Bending,” Microelectron. Reliab., 44 (12), pp. 1977–1983.

Suwa, T., and Hadim, H., 2007, “Multidisciplinary Electronic Package Design and Optimization Methodology Based on Genetic Algorithm,” IEEE Trans. Adv. Packag., 30 (3), pp. 402–410.

Xiong, G., Lu, M., Chen, C.-L., Wang, B. P., and Kehl, D., 2001, “Numerical Optimization of a Power Electronics Cooling Assembly,” "*Proceedings of the IEEE APEC*", Anaheim, CA.

Cheng, Y.-H., and Lin, W.-K., 2005, “Geometric Optimization of Thermoelectric Coolers in a Confined Volume Using Genetic Algorithms,” Appl. Therm. Eng.

[CrossRef], 25 (17-18), pp. 2983–2997.

Cimtalay, S., Peak, R. S., and Fulton, R. E., 1996, “Optimization of Solder Joint Fatigue Life Using Product Model-Based Analysis Models,” "*Proceedings of the ASME International Mechanical Engineering Congress and Exposition*", Atlanta, GA.

Stoyanov, S., Bailey, C., and Cross, M., 2001, “Integrating Computational Mechanics and Numerical Optimization for the Design of Material Properties in Electronic Packages,” "*Proceedings of the Conference on Computational Modeling of Materials, Minerals and Metals*", San Diego, CA.

Stoyanov, S., Bailey, C., and Lu, H., 2001, “Optimization Tools for Flip-Chip Design,” "*Proceedings of the ASME InterPACK*", Kauai, HI.

Stoyanov, S., and Bailey, C., 2003, “Optimisation and Finite Element Analysis for Reliable Electronic Packaging,” "*Proceedings of the EuroSIME*", Aix-en-Provence, France.

Meinzer, S., Quinte, A., Gorges-Schleuter, M., Jakob, W., Suss, W., and Eggert, H., 1996, “Simulation and Design Optimization of Microsystems Based on Standard Simulators and Adaptive Search Techniques,” "*Proceedings of the Design Automation Conference*".

Wu, W., Dunlop, J. B., Collocott, S. J., and Kalan, B. A., 2003, “Design Optimization of a Switched Reluctance Motor by Electromagnetic and Thermal Finite-Element Analysis,” IEEE Trans. Magn.

[CrossRef], 39 (5), pp. 3334–3336.

Momen, M. F., and Husain, I., 2003, “Optimizing the Design and Performance of a Switched Reluctance Machine Using Lumped Parameter Thermal Model,” "*Proceedings of the International Electric Machines and Drives Conference*".

Icoz, T., and Jaluria, Y., 2006, “Design Optimization of Size and Geometry of Vortex Promoter in a Two-Dimensional Channel,” ASME J. Heat Transfer

[CrossRef], 128 (10), pp. 1081–1092.

Deshpande, A. M., Subbarayan, G., and Mahajan, R. L., 1996, “Global Approximation Concepts for Optimal Design of Electronic Packages,” "*Proceedings of the ASME International Mechanical Engineering Congress and Exhibition*", Atlanta, GA.

Calmidi, V. V., and Mahajan, R. L., 1998, “Optimization for Thermal and Electrical Wiring for a Flip-Chip Package Using Physical-Neural Network Modeling,” IEEE Trans. Compon., Packag., Manuf. Technol., Part C

[CrossRef], 21 (2), pp. 111–117.

Sridhar, S., and Eggink, H. J., 1999, “Dealing With Uncertainty in Power Loss Estimates in Thermal Design of Power Electronic Circuits,” "*Proceedings of the Industry Applications Conference*", Phoenix, AZ.

Zhang, G. Q., Tay, A. A. O., Ernst, L. J., Liu, S., Qian, Z. F., Bressers, H. J. L., and Janssen, J., 2001, “Virtual Thermo-Mechanical Prototyping of Electronic Packaging Challenges in Material Characterization and Modeling,” "*Proceedings of the Electronic Components and Technology Conference*", Orlando, FL.

Khalilollahi, A., and Warley, R. L., 2005, “Thermal Stress Reduction and Optimization for Orthotropic Composite Boards,” "*Proceedings of the ASME Summer Heat Transfer Conference*", San Francisco, CA.

Khalilollahi, A., Warley, R. L., and Onipede, O., 2005, “Thermal Reliability Design and Optimization for Multilayer Composite Electronic Boards,” "*Proceedings of the ASME International Mechanical Engineering Congress and Exposition*", Orlando, FL.

Wu, X., Qian, Z., and Wang, Y., 2005, “Integrated Reliability Solutions for New Component Development and Designs Optimization,” "*Proceedings of the ASME International Mechanical Engineering Congress and Exposition*", Orlando, FL.

Chang, C.-L., and Lin, W.-S., 2003, “Robust Multiple Criteria Optimization of Thermally Enhanced PQFP,” J. Chin. Soc. Mech. Eng. Trans. Chin. Inst. Eng. Ser. C, 24 (1), pp. 73–80.

Tsai, C.-H., and Kang, S.-M. S., 1999, “Macrocell Placement With Temperature Profile Optimization,” "*Proceedings of the ISCAS*", Orlando, FL.

Tsai, C.-H., and Kang, S.-M., 2000, “Substrate Thermal Model Reduction for Efficient Transient Electrothermal Simulation,” "*Proceedings of the IEEE Mixed-Signal Design, SSMSD*", San Diego, CA.

Chen, G., and Sapatnekar, S., 2003, “Partition-Driven Standard Cell Thermal Placement,” "*Proceedings of the International Symposium on Physical Design*", Monterey, CA.

Suwa, T., and Hadim, H., 2006, “Multidisciplinary Heat Generating Cell Placement Optimization Using Genetic Algorithm and Artificial Neural Networks,” "*Proceedings of the AIAA/ASME Joint Thermophysics and Heat Transfer Conference*", San Francisco, CA.

Goplen, B., and Sapatnekar, S., 2003, “Efficient Thermal Placement of Standard Cells in 3D ICs Using a Force Directed Approach,” "*Proceedings of the International Conference on Computer Aided Design*", San Jose, CA.

Balakrishnan, K., Nanda, V., Easwar, S., and Lim, S. K., 2005, “Wire Congestion and Thermal Aware 3D Global Placement,” "*Proceedings of the Asia and South Pacific Design Automation Conference*".

Hung, W., Addo-Quaye, C., Theocharides, T., Xie, Y., Vijakrishnan, N., and Irwin, M. J., 2004, “Thermal-Aware IP Virtualization and Placement for Networks-On-Chip Architecture,” "*Proceedings of the IEEE International Conference Computer Design: VLSI in Computers and Processors*".

Sankaranarayanan, K., Velusamy, S., Stan, M. R., and Skadron, K., 2005, “A Case for Thermal-Aware Floorplanning at the Microarchitectural Level,” The Journal of Instruction-Level Parallelism, 8 , pp. 1–16,

http:// www.jilp.org/vol7/v7paper15.pdf.

Hung, W.-L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T., and Irwin, M. J., 2005, “Thermal-Aware Floorplanning Using Genetic Algorithms,” "*Proceedings of the International Symposium Quality of Electronic Design*", San Jose, CA.

Sato, T., Ichimiya, J., Ono, N., Hachiya, K., and Hashimoto, M., 2005, “On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design,” IEICE Trans. Fundamentals, E88-A (12), pp. 3382–3388.

Cong, J., Wei, J., and Zhang, Y., 2004, “A Thermal-Driven Floorplanning Algorithm for 3D ICs,” "*Proceedings of the IEEE/ACM International Conference on Computer Aided Design*", Santa Clara, CA.

Cong, J., and Zhang, Y., 2005, “Thermal-Driven Multilevel Routing for 3-D ICs,” "*Proceedings of the Asia South Pacific Design Automation Conference*", Shanghai, China.

Goplen, B., and Sapatnekar, S. S., 2006, “Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives,” IEEE Trans. Comput.-Aided Des.

[CrossRef], 25 (4), pp. 692–709.

Chao, K. Y., and Wong, D. F., 1995, “Thermal Placement for High-Performance Multichip Modules,” "*Proceedings of the IEEE International Conference Computer Design*", Austin, TX.

Lampaert, K., Gielen, G., and Sansen, W., 1997, “Thermally Constrained Placement of Smart-Power IC’s and Multi-Chip Modules,” "*Proceedings of the IEEE SEMI-THERM XIII*", Austin, TX.

Beebe, C., Carothers, J. D., and Ortega, A., 1999, “Object-Oriented Thermal Placement Using an Accurate Heat Model,” "*Proceedings of the HICSS-32*", Maui, HI.

Beebe, C., Carothers, J. D., and Ortega, A., 2000, “MCM Placement Using a Realistic Thermal Model,” "*Proceedings of the Great Lakes Symposium on VLSI*", Chicago, IL.

Lee, J., Chou, J.-H., and Fu, S.-L., 1995, “Reliability and Wirability Optimizations for Module Placement on a Convectively Cooled Printed Wiring Board,” Integr., VLSI J.

[CrossRef], 18 (2-3), pp. 173–186.

Mihan, K. K., Stacey, B. J., and Montor, T., 1995, “Interdisciplinary Design Optimization for High-Speed Packages and Interconnects,” "*Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering*", Montreal, Canada.

Queipo, N. V., and Gil, G. F., 2000, “Multiobjective Optimal Placement of Convectively and Conductively Cooled Electronic Components on Printed Wiring Boards,” ASME J. Electron. Packag.

[CrossRef], 122 (2), pp. 152–159.

Queipo, N. V., and Gil, G. F., 1997, “Multiobjective Optimization of Component Placement on Planar Printed Wiring Boards,” "*Proceedings of the IEEE SEMI-THERM XIII*", Austin, TX.

Queipo, N. V., Humphrey, J. A. C., and Ortega, A., 1996, “Multiobjective Optimization of Component Placement on Printed Wiring Boards,” "*Proceedings of the IEEE I-THERM V*", Orlando, FL.

Iwata, Y., Hayashi, S., Satoh, R., and Fujmoto, K., 2005, “Circuit-Thermal Collaboration Design Method for Outline Design Stage of Mobile Terminal,” "*Proceedings of the ASME InterPACK*", San Francisco, CA.

Deb, K., Jain, P., Gupta, N. K., and Maji, H. K., 2004, “Multiobjective Placement of Electronic Components Using Evolutionary Algorithms,” IEEE Trans. Compon. Packag. Technol., 27 (3), pp. 480–492.

Suwa, T., and Hadim, H., 2007, “Multidisciplinary Placement Optimization of Heat Generating Electronic Components on Printed Circuit Boards,” ASME J. Electron. Packag.

[CrossRef], 129 (1), pp. 90–97.

Suwa, T., and Hadim, H., 2007, “Multidisciplinary Placement Optimization of Heat Generating Electronic Components on a Printed Circuit Board in an Enclosure,” IEEE Trans. Compon. Packag. Technol., 30 (3), pp. 402–410.

Gopinath, D., Joshi, Y. K., and Azarm, S., 2001, “Multi-Objective Placement Optimization of Power Electronic Devices on Liquid Cooled Heat Sinks,” "*Proceedings of the Annual IEEE Symposium*", San Jose, CA.

Gopinath, D., Joshi, Y., and Azarm, S., 2005, “An Integrated Methodology for Multiobjective Optimal Component Placement and Heat Sink Sizing,” IEEE Trans. Compon. Packag. Technol., 28 (4), pp. 869–876.

Campbell, I. M., Amon, H. C., and Cagan, J., 1997, “Optimal Three-Dimensional Placement of Heat Generating Electronic Components,” ASME J. Electron. Packag.

[CrossRef], 119 (2), pp. 106–113.

Campbell, I. M., Cagan, J., Amon, H. C., and Szykman, S., 1995, “Electronic Component Placement Using Simulated Annealing Under Thermal Constraints,” "*Proceedings of the ASME International Mechanical Engineering Congress and Exposition*", San Francisco, CA.

Jackson, B., and Norgard, J., 2002, “A Stochastic Optimization Tool for Determining Spacecraft Avionics Box Placement,” "*Proceedings of the IEEE Aerospace Conference*", Big Sky, MT.

Kaczorowski, P. R., Joshi, Y., and Azarm, S., 2003, “Multi-Objective Design of Liquid Cooled Power Electronic Modules for Transient Operation,” "*Proceedings of the IEEE SEMI-THERM*", San Jose, CA.

Lee, J., and Chou, J.-H., 1996, “Hierarchical Placement for Power Hybrid Circuits Under Reliability and Wireability Constraints,” IEEE Trans. Reliab.

[CrossRef], 45 , pp. 200–207.

Huang, Y., and Fu, S., 2000, “Thermal Placement Design for MCM Applications,” ASME J. Electron. Packag.

[CrossRef], 122 (2), pp. 115–120.

Huang, Y.-J., Fu, S.-L., Jen, S.-L., and Guo, M.-H., 2001, “Fuzzy Thermal Modeling for MCM Placement,” Microelectron. J.

[CrossRef], 32 (10-11), pp. 863–868.

Huang, Y.-J., and Guo, M.-H., 2001, “Fuzzy Thermal Placement for Multichip Module Applications,” Fuzzy Sets Syst.

[CrossRef], 122 (2), pp. 185–194.

Lee, J., 2003, “Thermal Placement Algorithm Based on Heat Conduction Analogy,” IEEE Trans. Compon. Packag. Technol.

[CrossRef], 26 (2), pp. 473–482.

Lee, J., 2005, “Reliability and Wireability Optimizations for Chip Placement on Multichip Modules,” IEEE Trans. Electron. Packag. Manuf.

[CrossRef], 28 (2), pp. 133–141.

Chu, C. C. N., and Wong, D. F., 1998, “A Matrix Synthesis Approach to Thermal Placement,” IEEE Trans. Comput.-Aided Des., 17 (11), pp. 1166–1174.

Newbould, R. D., and Carothers, J. D., 2003, “Cluster Growth Revisited: Fast, Mixed-Signal Placement of Blocks and Gates,” "*Proceedings of the Southwest Symposium Mixed-Signal Design*", Las Vegas, NV.

Kaisare, A., Agonafer, D., Haji-Shiekh, A., Chriysler, G., and Mahajan, R., 2005, “Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die,” "*Proceedings of the ASME InterPack*", San Francisco, CA.

Miettinen, K., 1999, "*Nonlinear Multiobjective Optimization*", Springer, Boston.

Deb, K., Pratap, A., Agarwal, S., and Meyarivan, T., 2002, “A Fast and Elitist Multiobjective Genetic Algorithm: NSGA-II,” IEEE Trans. Evol. Comput.

[CrossRef], 6 (2), pp. 182–197.

Icoz, T., and Jaluria, Y., 2005, “Optimization of Vortex Promoter Design Using a Dynamic Data Driven Approach,” "*Proceedings of the ASME Summer Heat Transfer Conference*", San Francisco, CA.