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Research Papers

A Compact Approach to On-Chip Interconnect Heat Conduction Modeling Using the Finite Element Method

[+] Author and Article Information
Siva P. Gurrum

Semiconductor Packaging Technology Research, Texas Instruments Incorporated, Dallas, TX 75243

Yogendra K. Joshi

G. W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332

William P. King

Deparment of Mechanical Science and Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801

Koneru Ramakrishna, Martin Gall

Package Material Technology Development, Analog & Mixed Signal Technologies, Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, TX 78735

J. Electron. Packag 130(3), 031001 (Jul 29, 2008) (8 pages) doi:10.1115/1.2957318 History: Received March 13, 2006; Revised October 23, 2007; Published July 29, 2008

Over upcoming electronics technology nodes, shrinking feature sizes of on-chip interconnects and correspondingly higher current densities are expected to result in higher temperatures due to self-heating. This study describes a finite element based compact thermal modeling approach to investigate the effects of Joule heating on complex interconnect structures. In this method, interconnect cross section is assumed to be isothermal and conduction along the interconnect is retained. A composite finite element containing both metal and dielectric regions is used to discretize the interconnect stack. The compact approach predicts the maximum temperature rise in the metal to within 5–10% of the detailed numerical computations, while requiring only a fraction of elements. Computational time for the compact model solution is several seconds, versus many hours for the detailed solutions obtained through successive mesh refinement until grid independence is achieved. For a comparable number of elements, the compact model is in general much more accurate than the traditional finite element approach. To validate the simulations, temperature rise in a 500-link two-layer interconnect with a via layer was measured at several current densities. The compact method predicts the temperature rise of the 500-link chain to within 5% of the measurements thereby validating the method. The approach described here could be an efficient technique for full chip Joule heating simulations and for clock signal propagation simulations, which are performed as part of designing next generation chip architectures.

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Copyright © 2008 by American Society of Mechanical Engineers
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Figures

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Figure 2

A conventional element and a compact element are contrasted at the bottom. The compact element has shaded metallic regions together with dielectric regions. The interpolating function for Node 1 in both approaches is shown above. In the compact element case, this function ignores temperature drop across the metallic region.

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Figure 3

(a) A set of uniformly spaced interconnects embedded in the dielectric is shown on the top. Different meshes used in the traditional finite element technique (denoted FEM) and compact model technique (CM) are shown below. The number of elements is shown on a per pitch basis. (b) Percentage error in FEM and CM of (a) when compared with detailed finite element simulations. (c) Percentage error with two element compact model as dielectric-to-metal thermal conductivity ratio increases for P∕W=2.

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Figure 4

A comparison of observed computational cost scaling versus a linear scaling as the number of elements increases. Actual computational cost scales as Nel1.46 for the simple structure shown in Fig. 3 (Nel is the number of elements). This means that a fourfold increase in the number of elements requires ∼7.6 times more computational time.

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Figure 5

Temperature profile for the structure shown in Fig. 3 when only the leftmost interconnect is generating heat for various pitches. The flat regions in the detailed model profiles correspond to interconnects and are a result of high metal thermal conductivity.

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Figure 6

(a) A schematic of the three-dimensional interconnect with vias near the ends along with the location of nodes. (b) Temperature profiles along the interconnect for different lengths. Pitch P=4W for these simulations.

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Figure 7

(a) A schematic of the long chain of interconnects and vias. (b) Temperature map of the heat-generating region for a current density of 23.8MA∕cm2. (c) Schematic of different layers from the bottom of silicon wafer until Metal Level 1.

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Figure 8

Experimental and numerical temperature rise of the interconnect/via chain shown in Fig. 7. The error bars for the highest current density data point are obtained by including property uncertainties.

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Figure 1

(a) A schematic of interconnect stack with metal lines and vias adapted from Ref. 1. (b) A common idealization of uniformly spaced interconnects.

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