The physics explored in this investigation enables short-time scale dynamic phenomenon to be correlated with package failure modes such as solder ball cracking and interlayer debond. It is found that although epoxy-based underfills with nanofillers are shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity is ineffective in attenuating short-time scale propagating shock waves. In addition, the inclusion of Cu interconnecting layers in flip chip area arrays is found to perform significantly better than Al layers in suppressing short-time scale effects. Results reported herein suggest that, if improved flip chip reliability is to be achieved, the compositions of all packaging constituent materials need be formulated to have well-defined short-time scale and long-time scale properties. Chip level circuit design layout also needs be optimized to either discourage or negate short-time wave propagation. The knowledge base established is generally applicable to high performance package configurations of small footprint and high clock speed. The approach along with the numerical procedures developed for the investigation can be a practical tool for realizing better device reliability and thus high manufacturing yield.