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Research Papers

On Failure Mechanisms in Flip Chip Assembly—Part 2: Optimal Underfill and Interconnecting Materials

[+] Author and Article Information
Yoonchan Oh, Hung-Jue Sue

Mechanical Engineering Department, Texas A&M University, College Station, TX 77843-3123

C. Steve Suh

Mechanical Engineering Department, Texas A&M University, College Station, TX 77843-3123ssuh@tamu.edu

J. Electron. Packag 130(2), 021009 (May 09, 2008) (8 pages) doi:10.1115/1.2912209 History: Received February 21, 2007; Revised September 26, 2007; Published May 09, 2008

The physics explored in this investigation enables short-time scale dynamic phenomenon to be correlated with package failure modes such as solder ball cracking and interlayer debond. It is found that although epoxy-based underfills with nanofillers are shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity is ineffective in attenuating short-time scale propagating shock waves. In addition, the inclusion of Cu interconnecting layers in flip chip area arrays is found to perform significantly better than Al layers in suppressing short-time scale effects. Results reported herein suggest that, if improved flip chip reliability is to be achieved, the compositions of all packaging constituent materials need be formulated to have well-defined short-time scale and long-time scale properties. Chip level circuit design layout also needs be optimized to either discourage or negate short-time wave propagation. The knowledge base established is generally applicable to high performance package configurations of small footprint and high clock speed. The approach along with the numerical procedures developed for the investigation can be a practical tool for realizing better device reliability and thus high manufacturing yield.

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Copyright © 2008 by American Society of Mechanical Engineers
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References

Figures

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Figure 11

dS22∕dt power density wave at Location 1 of the third solder joint

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Figure 12

Accumulated damage by dS22∕dt at locations within the third (left) and fourth (right) solder joints

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Figure 13

Accumulated damage by dS12∕dt at locations within the third (left) and fourth (right) solder joint

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Figure 10

Flip chip configuration (Cu top layer) and locations for accumulated damage estimation

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Figure 9

Accumulated damage by dS22∕dt at locations within the third solder joint with various silica filler contents

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Figure 8

Accumulated damage by dS11∕dt at locations within the third solder joint (elastic underfill versus viscoelastic underfill)

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Figure 7

Accumulated damage by dS12∕dt at locations within underfill (elastic underfill versus viscoelastic underfill)

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Figure 6

Accumulated damage by dS11∕dt at locations within underfill (elastic underfill versus viscoelastic underfill)

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Figure 5

dS11∕dt (left) and dS12∕dt (right) power density waveforms at Location U-1 (elastic underfill versus viscoelastic underfill)

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Figure 4

Selected locations within underfill and the third solder joint for short-time scale waveform acquisition

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Figure 3

CTE (top), Young’s modulus (middle), and solder fatigue life (bottom) corresponding to Underfills A, B, and C as functions of weight percent of filler

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Figure 2

Saturated inelastic strain (top) and predicted fatigue life (bottom) as functions of E and CTE

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Figure 1

Thermal cycling temperature profile

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