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Research Papers

On Failure Mechanisms in Flip Chip Assembly—Part 1: Short-Time Scale Wave Motion

[+] Author and Article Information
Yoonchan Oh, Hung-Jue Sue

Mechanical Engineering Department, Texas A&M University, College Station, TX 77843-3123

C. Steve Suh

Mechanical Engineering Department, Texas A&M University, College Station, TX 77843-3123ssuh@mengr.tamu.edu

J. Electron. Packag 130(2), 021008 (May 09, 2008) (11 pages) doi:10.1115/1.2912188 History: Received February 21, 2007; Revised September 26, 2007; Published May 09, 2008

The demand for higher clock speed and larger current magnitude in high-performance flip chip packaging configurations of small footprint has raised the concern over rapid thermal transients and large thermal spatial gradients that could severely compromise package performance. This paper explores coupled electrical-thermal-mechanical multiphysics to evaluate the concern and to establish the knowledge base necessary for improving flip chip reliability. It is found that within the first few hundreds of nanoseconds after power-on, there are fast-attenuating, dispersive stress waves of extremely high frequency propagating in the package. The concepts of high cycle fatigue, power density, and joint time-frequency analysis are employed to characterize the waves along with the various damage modes resulting from the propagation of these short-lived dynamical disturbances in bulk materials and along bimaterial interfaces. A qualitative measure for failure is developed to evaluate the extent of damage inflicted by short-time wave motion. Damages identified in this study are in agreement with physical failure modes commonly seen in industry, thus implying that micron scale cracks or interfacial adhesion flaws initiated at the short-time scale would be further propagated by the coefficient of thermal expansion induced thermal stresses at the long-time scale and result in eventual electrical disruptions.

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Copyright © 2008 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Flip chip configuration (top, not to scale) and its finite element mesh (bottom, to scale) with stress components at Location 2 [22]

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Figure 2

Heat flux in 2-direction at the Si-Al-underfill interface next to the corner of the third solder joint

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Figure 3

Stress waveforms at Location 2 (left) and at Location 3 (right)

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Figure 4

Frequency responses at Location 2 (left) and Location 3 (right)

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Figure 5

S-N curve (top) and N–power density curve (bottom) of eutectic solder

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Figure 6

Normal and shear power density waves at Location 1

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Figure 7

STFT analysis of dS22∕dt (top) and dS12∕dt (bottom) waves at Location 1

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Figure 8

Accumulated damage evaluation

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Figure 9

STFT coefficient of dS22∕dt wave at Location 3 at t=1.3×10−7s

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Figure 10

Locations for accumulated damage estimation

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Figure 11

Accumulated damage by dS22∕dt along time at various locations within the third (top) and fourth (bottom) solder joints

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Figure 12

Selected waveform acquisition locations for interfacial delamination damage evaluation

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Figure 13

Accumulated damage by dS12∕dt along time at various interfacial locations between Al and other meterials

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